DDR SDRAM memory controller with multiple dependency request architecture and intelligent requestor interface
View Patent ↗A controller for a double data rate synchronous dynamic random access memory (SDRAM) includes an address storage block comprising an address storage register for each of a plurality of priority levels for receiving a memory address of a request from an incoming command queue for each of a plurality of priority levels and a priority logic block coupled to the address storage block wherein the priority logic block comprises a first priority register for storing a register number field for each of the plurality of priority levels, a second priority register for storing a request valid field for each of the plurality of priority levels, and a third priority register for storing a state machine address field for each of the plurality of priority levels.
1. A controller for a double data rate synchronous dynamic random access memory (SDRAM) comprising:
an address storage block comprising an address storage register for each of a plurality of priority levels for receiving a memory address of a request from an incoming command queue for each of a plurality of priority levels; and
a priority logic block coupled to the address storage block wherein the priority logic block comprises a first priority register for storing a register number field for each of the plurality of priority levels, a second priority register for storing a request valid field for each of the plurality of priority levels, and a third priority register for storing a state machine address field for each of the plurality of priority levels.
2. The controller of claim 1 wherein each register number field contains a register number of a corresponding address storage register.
3. The controller of claim 2 wherein each request valid field indicates whether a corresponding register number field contains the register number associated with a request granted by one of a plurality of bank state machines.
4. The controller of claim 3 wherein each state machine address field identifies one of the plurality of bank state machines to which a request from the incoming command queue is assigned.
5. The controller of claim 3 further comprising a request selection block for receiving a command associated with the request granted by one of the plurality of bank state machines for each of the plurality of priority levels and for selecting which command to send to the SDRAM.
6. The controller of claim 5 wherein the request selection block selects the command associated with the request having highest priority if the command is a Read, Write, Activate or Precharge and if all timing constraints of the SDRAM are satisfied.
7. The controller of claim 6 wherein the request selection block selects the command associated with the request having lower priority than the request having highest priority if all timing constraints of the SDRAM are not satisfied.
8. The controller of claim 6 wherein the request selection block sends a NOP command to the SDRAM if no requests are active.
9. The controller of claim 1 further comprising a shift logic block for shifting the first priority register, the second priority register, and the third priority register according to one of a plurality of shift cycles selected from a dependency table entry wherein the dependency table entry is a function of a current value of each request valid field.
10. The controller of claim 9 wherein a first shift cycle of the plurality of shift cycles comprises a circular shift by one field position of each register number field in the first priority register, each request valid field in the second priority register, and each state machine address field in the third priority register.
11. The controller of claim 10 wherein a second shift cycle of the plurality of shift cycles comprises a circular shift by one field position of at least two register number fields in the first priority register, at least two request valid fields in the second priority register, and at least two state machine address fields in the third priority register.
12. A method for controlling a double data rate synchronous dynamic random access memory (SDRAM) comprising:
receiving a memory address of a request from an incoming command queue in an address storage register for each of a plurality of priority levels;
storing a register number field for each of the plurality of priority levels in a first priority register;
storing a request valid field for each of the plurality of priority levels in a second priority register; and
storing a state machine address field for each of the plurality of priority levels in a third priority register.
13. The method of claim 12 wherein each register number field contains a register number of a corresponding address storage register.
14. The method of claim 13 further comprising indicating in each request valid field whether a corresponding register number field contains the register number associated with a request granted by one of a plurality of bank state machines.
15. The method of claim 14 further comprising identifying in each state machine address field one of the plurality of bank state machines to which a request from the incoming command queue is assigned.
16. The method of claim 14 further comprising receiving a command associated with the request granted by one of the plurality of bank state machines for each of the plurality of priority levels and selecting which command to send to the SDRAM.
17. The method of claim 16 further comprising selecting the command associated with the request having highest priority if the command is a Read, Write, Activate or Precharge and if all timing constraints of the SDRAM are satisfied.
18. The method of claim 17 further comprising selecting the command associated with the request having lower priority than the request having highest priority if all timing constraints of the SDRAM are not satisfied.
19. The method of claim 17 further comprising sending a NOP command to the SDRAM if no requests are active.