IP Library Granted Patent US 6,852,621
Granted Patent B2
US 6,852,621 · App. 10/698,432 · Granted Feb 8, 2005

Semiconductor device and manufacturing method therefor, circuit board, and electronic equipment

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,852,621
App. No.
10/698,432
Granted
Feb 8, 2005
Kind
B2
Abstract

A method of manufacturing a semiconductor device comprises a step of forming a through-hole in a semiconductor chip having an electrode and forming a conductive layer on a region comprising an inner side of the through-hole. An intermediate portion of the through-hole is formed to be larger than an edge portion thereof, and the conductive layer is formed by electroless plating.

Claims (24)

1. A method of manufacturing a semiconductor device, the method comprising:

(a) forming a hole in an electrode, the electrode formed on a semiconductor element;

(b) after the hole is formed in the electrode, forming a through-hole in the semiconductor element so as to be connected to the hole; and

(c) forming a conductive layer in a region including an inner side of the through-hole.

2. The method of manufacturing a semiconductor device as defined in claim 1 , wherein in the (c) step the conductive layer is formed on at least part of the electrode.

3. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the through-hole comprises an edge portion and an intermediate portion of which width is larger than a width of the edge portion.

4. The method of manufacturing a semiconductor device as defined in claim 3 , wherein:

all portions of the intermediate portion are formed at substantially the same width; and

the through-hole comprises a tapered portion connecting the edge portion with the intermediate portion.

5. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the through-hole is formed in the (b) step by first forming a pinhole of a width smaller than a width of the through-hole, then expanding the pinhole.

6. The method of manufacturing a semiconductor device as defined in claim 5 , wherein a cavity is formed in the (b) step at a position at which the through-hole is to be formed, then the pinhole is formed by positioning at the cavity.

7. The method of manufacturing a semiconductor device as defined in claim 5 , wherein the pinhole is formed by a laser beam, then the pinhole is enlarged by wet etching.

8. The method of manufacturing a semiconductor device as defined in claim 1 , the method further comprising a step of forming an electrical connection portion.

9. The method of manufacturing a semiconductor device as defined in claim 8 , wherein the electrical connection portion is formed as part of the conductive layer in the (c) step.

10. The method of manufacturing a semiconductor device as defined in claim 1 , the method further comprising a step of forming an insulation film on an inner surface of the through-hole, after the (b) step and before the (c) step, wherein the conductive layer is formed on the insulation film in the (c) step.

11. The method of manufacturing a semiconductor device as defined in claim 5 , the method further comprising a step of forming an insulation film on a inner surface of the through-hole, after the (b) step and before the (c) step, wherein the conductive layer is formed on the insulation film in the (c) step.

12. The method of manufacturing a semiconductor device as defined in claim 7 , the method further comprising a step of forming an insulation film on an inner surface of the through-hole, after the (b) step and before the (c) step, wherein the conductive layer is formed on the insulation film in the (c) step.

13. The method of manufacturing a semiconductor device as defined in claim 12 , wherein the insulation film is formed by chemical vapor deposition.

14. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the conductive layer is formed by electroless plating.

15. The method of manufacturing a semiconductor device as defined in claim 14 , wherein a catalyst is exposed in at least a region in which the conductive layer is formed, electroless plating is performed to extract a conductive material in the exposed region of the catalyst, and the conductive layer is formed from the conductive material.

16. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the semiconductor element is a semiconductor chip.

17. The method of manufacturing a semiconductor device as defined in claim 1 , wherein the semiconductor element is part of a semiconductor wafer.

18. A method of manufacturing a semiconductor device, the method comprising a step of stacking semiconductor devices that were formed by the method of manufacturing a semiconductor device as defined in claim 1 , and electrically connecting together the conductive layer of each of upper and lower semiconductor devices.

19. The method of manufacturing a semiconductor device as defined in claim 17 , further comprising a step of cutting the semiconductor wafer into pieces.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2017
From: SEIKO EPSON CORPORATION
To: ADVANCED INTERCONNECT SYSTEMS LIMITED
Reel/Frame 044938/0869 →