Reference cells for TCCT based memory cells
View Patent ↗A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cell' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of th current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.
1. A reference cell for determining a state stored in a first memory cell that produces a first current, comprising:
a second memory cell that produces a second current; and
a current reduction element that accepts the second current and delivers a third current, and
is coupled to the second memory cell,
is configured to receive a reference voltage that is a function of at least the first and the third currents, and
has a resistance that varies as a function of the reference voltage.
2. The reference cell of claim 1 , wherein the second memory cell is a TCCT based memory cell.
3. The reference cell of claim 1 , wherein the second memory cell is an SRAM memory cell.
4. The reference cell of claim 1 , wherein the second memory cell is an MRAM memory cell.
5. The reference cell of claim 1 , wherein the second memory cell is a memory cell with a floating gate.
6. The reference cell of claim 1 , wherein the current reduction element is a transistor.
7. A reference cell for a TCCT based memory cell that produces a first current, comprising:
an NDR device that produces a second current, including
a first end configured to have a first voltage applied thereto,
a second end,
a doped semiconductor layer between the first and second ends, and
a gate-like device disposed adjacent to the doped semiconductor layer;
a first word line;
a second word line coupled to the gate-like device;
a pass transistor including
a drain,
a source coupled to the second end, and
a gate coupled to the first word line;
a bit line; and
a current reduction element coupled between the bit line and the drain accepts the second current and delivers a third current, the current reduction element is configured to receive a reference voltage that is a function of at least the first and the third currents and has a resistance that varies as a function of the reference voltage.
8. The reference cell of claim 7 wherein the current reduction element is a second pass transistor including a gate having the reference voltage applied thereto.