IP Library Granted Patent US 6,943,434
Granted Patent B2
US 6,943,434 · App. 10/678,010 · Granted Sep 13, 2005

Method for maintaining solder thickness in flipchip attach packaging processes

Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 6,943,434
App. No.
10/678,010
Granted
Sep 13, 2005
Kind
B2
Abstract

A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.

Claims (54)

1. A method for forming a semiconductor package, the method

comprising: providing a die with a metal stud on a bond pad;

providing a leadframe containing a plurality of leads, the leadframe containing a solderable area surrounded by a solder dam;

providing a solder paste in or on the solderable area;

attaching the die and the leadframe; and

molding a molding material around a portion of the die and a portion of the leadframe.

2. The method of claim 1 , wherein the metal stud contains substantially no Pb.

3. The method of claim 2 , wherein the amount of Pb in the metal stud is less than about 1 ppm.

4. The method of claim 1 , including attaching the die to the leadframe by flipping the die and contacting the metal stud with the solder paste.

5. The method of claim 1 , wherein the solderable area contains a pad comprising a non-oxidizable metal.

6. The method of claim 5 , wherein the solder dam comprises a metal oxide or polymer material.

7. The method of claim 6 , including providing the metal oxide material by providing a metal and then oxidizing the metal.

8. The method of claim 6 , including providing the polymeric material by screen printing.

9. The method of claim 1 , including molding by using a film assisted molding process.

10. The method of claim 1 , further including re-flowing the solder paste after attaching the die and the leadframe.

11. A method for forming a semiconductor package, the method comprising:

providing a die with a metal stud on a bond pad, the metal stud containing substantially no Pb;

providing a leadframe containing a plurality of leads, the leadframe containing a solderable area surrounded by a solder dam;

providing a solder paste in or on the solderable area;

attaching the die and the leadframe; and

molding a molding material around a portion of the die and a portion of the leadframe.

12. The method of claim 11 , wherein the amount of Pb in the metal stud is less than about 1 ppm.

13. The method of claim 11 , wherein the solderable area contains a pad comprising a non-oxidizable metal.

14. The method of claim 13 , wherein the solder dam comprises a metal oxide or polymer material.

15. The method of claim 14 , including providing the metal oxide material by providing a metal and then oxidizing the metal.

16. The method of claim 14 , including providing the polymeric material by screen printing.

17. The method of claim 11 , including molding by using a film assisted molding process.

18. The method of claim 11 , further including re-flowing the solder paste after attaching the die and the leadframe.

19. The method of claim 18 , further including providing the leadframe with a depression.

20. The method of claim 19 , wherein the depression restricts the flow of the solder paste during the reflow.

21. A method for forming a semiconductor package, the method comprising:

providing a die with a metal stud on a bond pad, the metal stud containing substantially no Pb;

providing a leadframe containing a solderable area surrounded by a solder dam, the solderable area containing a pad comprising a non-oxidizable metal and the solder dam comprising a metal oxide or polymer material;

providing a solder paste in or on the solderable area;

attaching the die and the leadframe; and

molding a molding material around a portion of the die and a portion of the leadframe.

22. A semiconductor package made by the method comprising:

providing a die with a metal stud on a bond pad;

providing a leadframe containing a plurality of leads, the leadframe containing a solderable area surrounded by a solder dam;

providing a solder paste in or on the solderable area;

attaching the die and the leadframe; and

molding a molding material around a portion of the die and a portion of the leadframe.

23. A semiconductor package made by the method comprising:

providing a die with a metal stud on a bond pad, the metal stud containing substantially no Pb,

providing a leadframe containing a plurality of leads, the leadframe containing a solderable area surrounded by a solder dam;

providing a solder paste in or on the solderable area;

attaching the die and the leadframe; and

molding a molding material around a portion of the die and a portion of the leadframe.

24. A semiconductor package made by the method comprising:

providing a die with a metal stud on a bond pad, the metal stud containing substantially no Pb;

providing a leadframe containing a solderable area surrounded by a solder dam, the solderable area containing a pad comprising a non-oxidizable metal and the solder dam comprising a metal oxide or polymer material;

providing a solder paste in or on the solderable area;

attaching the die and the leadframe; and

molding a molding material around a portion of the die and a portion of the leadframe.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2005
From: TANGPUZ, CONSUELO N.; MANATAD, ROMEL N.; RIOS, MARGIE R.; CRUZ, ERWIN VICTOR R.
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 016585/0855 →
Continuity (2)
Provisional Application 6041780000 · Oct 3, 2002
Related Publication 20040130009A1 · Jul 8, 2004