IP Library Granted Patent US 6,953,734
Granted Patent B2
US 6,953,734 · App. 10/735,742 · Granted Oct 11, 2005

Method for manufacturing shallow trench isolation in semiconductor device

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 6,953,734
App. No.
10/735,742
Granted
Oct 11, 2005
Kind
B2
Abstract

The method for manufacturing an STI in a semiconductor device with an enhanced gap-fill property and leakage property is disclosed by introducing a nitridation process instead of forming a liner nitride. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming an isolation trench with a predetermined depth in the semiconductor substrate; forming a wall oxide on the trench; forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; carrying out a nitridation process for forming a nitrided oxide; forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and planarizing a top face of the insulating layer.

Claims (29)

1. A method for manufacturing a shallow trench isolation (STI) in a semiconductor device, the method comprising the steps of:

a) preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof;

b) forming an isolation trench with a predetermined depth in the semiconductor substrate;

c) forming a wall oxide on the trench;

d) forming a liner oxide on the wall oxide and an exposed surface of the pad nitride;

e) carrying out a nitridation process for forming a nitrided oxide;

f) forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and

g) planarizing a top face of the insulating layer,

wherein the step e) is carried out in an annealing furnace or a rapid thermal process (RTP) by using a nitrogen-containing gas selected from the group consisting of N 2 O, NO and NH 3 , thereby forming the nitrided oxide between the liner oxide and the wall oxide.

2. The method as recited in claim 1 , wherein the step e) is carried out by using NO gas as a source gas at a temperature in a range of about 750° C. to about 850° C.

3. The method as recited in claim 1 , wherein the step e) is carried out by using NH 3 gas as a source gas at a temperature in a range of about 750° C. to about 850° C.

4. The method as recited in claim 1 , wherein the step e) is carried out by using N 2 O gas as a source gas at a temperature in a range of about 800° C. to about 950° C.

5. The method as recited in claim 1 , wherein the step d) is carried out by repeating a chemical vapor deposition (CVD) process for forming a plurality of interfaces on the wall oxide.

6. The method as recited in claim 1 , wherein the step c) is carried out by using dry oxidation process on condition that a process temperature is in the range of about 850° C. to about 950° C. and a chlorine gas is supplied with amount in the range of about 0.1% to about 10%.

7. The method as recited in claim 1 , wherein the step f) is carried out by using a material selected from the group consisting of a high density plasma (HDP) oxide, an advanced planarized layer (APL) and a spin on dielectric (SOD).

8. A method for manufacturing an STI in a semiconductor device, the method comprising the steps of:

a) preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof;

b) forming an isolation trench with a predetermined depth in the semiconductor substrate;

c) forming a wall oxide on the trench;

d) carrying out a nitridation process for forming a nitrided oxide on the wall oxide;

e) forming a liner oxide on the nitrided oxide;

f) forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and

g) planarizing a top face of the insulating layer,

wherein the step d) is carried out in an annealing furnace or a rapid thermal process (RTP) by using a nitrogen-containing gas selected from the group consisting of N 2 O, NO and NH 3 .

9. The method as recited in claim 8 , wherein the step c) is carried out by using dry oxidation process on condition that a process temperature is in the range of about 850° C. to about 950° C. and a chlorine gas is supplied with amount in the range of about 0.1% to about 10%.

10. The method as recited in claim 8 , wherein the step f) is carried out by using a material selected from the group consisting of an HDP oxide, an APL and an SOD.

11. The method as recited in claim 8 , wherein the step d) is carried out by using NO gas as a source gas at a temperature in a range of about 750° C. to about 850° C.

12. The method as recited in claim 8 , wherein the step d) is carried out by using NH 3 gas as a source gas at a temperature in a range of about 750° C. to about 850° C.

13. The method as recited in claim 8 , wherein the step d) is carried out by using N 2 O gas as a source gas at a temperature in a range of about 800° C. to about 950° C.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2003
From: LIM, JAE-EUN; SOHN, YONG-SUN
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 014803/0639 →
Priority Claims (1)
KR 10-2003-0051086 · Jul 24, 2003 · national
Continuity (1)
Related Publication 20050020027A1 · Jan 27, 2005