SAR data converter with unequal clock pulses for MSBS to allow for settling

1. A method for selectively switching capacitors in a SAR capacitor array that have a common plate thereof interfaced to the input of a comparator, comprising the steps of:

initiating a SAR compare cycle;

switching the other plates the capacitors to be disposed at either a first capacitor reference voltage or a second capacitor reference voltage in a combination and sequence of switching operations defined by a successive approximation search algorithm;

each switching operation in the sequence requiring, after the step of switching, a comparison of the voltage input to the comparator with a compare reference voltage after a predetermined settling time from the time the capacitor combination for the switching operation has been switched; and

controlling the duration of the settling time for each of the switching operations in the sequence such that at least two of the durations are different.

2. The method of claim 1 , wherein the step of controlling the duration of settling time for each switching operation comprises generating a clock with unequal cycles wherein at least one cycle in a clock sequence has a longer cycle than the remaining clock cycles in the clock cycle sequence.

3. The method of claim 2 , wherein at least two clock cycles have a longer duration than the remaining clock cycles in the sequence.

4. The method of claim 3 , wherein the at least two clock cycles have a substantially similar duration.

5. The method of claim 1 , wherein the first of the switching operations in the sequence is associated with a most significant bit (MSB) in the sequence, which associated first switching operation has a longer duration than at least one of the other switching operations in the associated SAR conversion cycle.

6. The method of claim 5 , wherein the second switching operation in the sequence is associated with a second MSB that immediately follows the first switching operation and the second switching operation has a duration substantially equal to that of the first switching operation.

7. The method of claim 5 , wherein the SAR capacitor array has a plurality of capacitors associated therewith of different sizes and the one of the capacitors associated with the first switching operation is the largest capacitor in the SAR capacitor array.

8. The method of claim 5 , wherein the last of the switching operations in the sequence has the shortest duration.

9. The method of claim 1 , wherein the step of initiating a SAR conversion cycle comprises impressing an input voltage to be converted to a digital value in the SAR conversion cycle across all of the capacitors in the SAR capacitor array during a tracking phase prior to the first switching operation in the sequence.

10. The method of claim 9 , wherein the step of switching the other plate of the capacitors between the first capacitor reference voltage and the second capacitor reference voltage comprises disposing one plate of a select one or ones of the plurality of capacitors to a potential equal to the first capacitor reference voltage and disposing the other plate of each of the remaining capacitors in the SAR capacitor array to a potential equal to the second capacitor reference voltage in accordance with the successive approximation search algorithm.

11. The method of claim 1 , wherein the second capacitor reference voltage comprises system ground.

12. A SAR switching control for selectively switching capacitors in a SAR capacitor array that have a common plate thereof interfaced to the input of a comparator, comprising:

a plurality of switches associated with the other plates of each of the capacitors;

a tracking controller for initiating a SAR compare cycle;

a switch controller for controlling said switches to switch the other plates of the capacitors to either a first capacitor reference voltage or a second capacitor reference voltage in a combination and sequence of switching operations defined by a successive approximation search algorithm, the combination associated with a digital value for the capacitors connected to the first capacitor reference voltage;

a latch for latching the output value of the comparator at the end of a comparison cycle wherein each switching operation in the sequence requiring, after switching by said switch controller, a comparison of the voltage input to the comparator with a compare reference voltage after a predetermined settling time, constituting the end of the comparison cycle, from the time the capacitor combination for the switching operation has been switched; and

a clock controller for controlling the duration of the settling time for each of the switching operations in the sequence such that at least two of the durations are different.

13. The switch controller of claim 12 , wherein the first of the switching operations in the sequence is associated with a most significant bit (MSB) in the sequence, which associated first switching operation has a longer duration than at least one of the other switching operations in the associated SAR conversion cycle.

14. The switch controller of claim 13 , wherein the SAR capacitor array has a plurality of capacitors associated therewith of different sizes and the one of the capacitors associated with the first switching operation is the largest capacitor in the SAR capacitor array.

15. The switch controller of claim 14 , wherein the last of the switching operations in the sequence has the shortest duration.

16. The switch controller of claim 13 , wherein the second switching operation in the sequence is associated with a second MSB that immediately follows the first switching operation and the second switching operation has a duration substantially equal to that of the first switching operation.

17. The switch controller of claim 12 , wherein said clock controller comprises a clock with unequal cycles wherein at least one cycle in a clock sequence has a longer cycle than the remaining clock cycles in the clock cycle sequence.

18. The switch controller of claim 17 , wherein at least two clock cycles have a longer duration than the remaining clock cycles in the sequence.

19. The switch controller of claim 18 , wherein the at least two clock cycles have a substantially similar duration.

20. The switch controller of claim 12 , wherein said SAR controller is operable to impress an input voltage to be converted to a digital value in the SAR conversion cycle across all of the capacitors in the SAR capacitor array during a tracking phase prior to the first switching operation in the sequence.

21. The switch controller of claim 20 , wherein said switch controller is operable to dispose the other plate of a select one or ones of the plurality of capacitors to a potential equal to the first capacitor reference voltage and dispose the other plate of each of the remaining capacitors in the SAR capacitor array to a potential equal to the second capacitor reference voltage in accordance with the successive approximation search algorithm.

22. The switch controller of claim 12 , wherein the second capacitor reference voltage comprises system ground.