Booster circuit, semiconductor device, and display device

1. A booster circuit including a plurality of capacitors, the booster circuit comprising:

first to M-th power supply lines (M is an integer greater than three);

first to (M−2)th boost capacitors, the j-th boost capacitor (1≦j≦M−2, j is an integer) being connected between the j-th power supply line and the (j+1)th power supply line in a first period, and connected between the (j+1)th power supply line and the (j+2)th power supply line in a second period which is subsequent to the first period; and

first to (M−3)th stabilization capacitors, the k-th stabilization capacitor (1≦k≦M−3, k is an integer) being connected between the (k+1)th power supply line and the (k+2)th power supply line, and storing an electric charge discharged from the k-th boost capacitor in the second period,

wherein a voltage obtained by multiplying a voltage between the first and second power supply lines (M−1) times is output between the first and M-th power supply lines.

2. The booster circuit as defined in claim 1 , further comprising:

an (M−2)th stabilization capacitor connected between the (M−1)th power supply line and the M-th power supply line,

wherein the (M−2)th stabilization capacitor stores an electric charge discharged from the (M−2)th boost capacitor in the second period.

3. The booster circuit as defined in claim 1 , comprising an output capacitor connected between the first power supply line and the M-th power supply line.

4. The booster circuit as defined in claim 1 , wherein the voltage between the first and second power supply lines is applied to each of the boost capacitors and each of the stabilization capacitors.

5. A booster circuit including a plurality of capacitors, the booster circuit comprising:

first to (N+1)th power supply lines (N is an integer greater than two);

first to 2N-th switching elements, one end of the first switching element being connected with the first power supply line, one end of the 2N-th switching element being connected with the (N+1)th power supply line, and the switching elements other than the first and 2N-th switching elements being connected in series between the other end of the first switching element and the other end of the 2N-th switching element;

first to (N−1)th boost capacitors, one end of each of the boost capacitors being connected with a j-th connection node (1≦j≦2N−3, j is an odd number) to which the j-th and (j+1)th switching elements are connected, and the other end of the boost capacitor being connected with a (j+2)th connection node to which the (j+2)th and (j+3)th switching elements are connected; and

first to (N−2)th stabilization capacitors, one end of each of the stabilization capacitors being connected with a k-th connection node (2≦k≦2N−4, k is an even number) to which the k-th and (k+1)th switching elements are connected, and the other end of the stabilization capacitor being connected with a (k+2)th connection node to which the (k+2)th and (k+3)th switching elements are connected,

wherein the switching elements are controlled so that one of the m-th switching element (1≦m≦2N−1, m is an integer) and the (m+1)th switching element is turned on, and a voltage obtained by multiplying a voltage between the first and second power supply lines N times is output between the first and (N+1)th power supply lines.

6. The booster circuit as defined in claim 5 , further comprising:

an (N−1)th stabilization capacitor connected between the N-th power supply line and the (N+1)th power supply line,

wherein the (N−1)th stabilization capacitor stores an electric charge discharged from the (N−1)th boost capacitor in the second period.

7. The booster circuit as defined in claim 5 , comprising an output capacitor connected between the first power supply line and the (N+1)th power supply line.

8. The booster circuit as defined in claim 5 , wherein the voltage between the first and second power supply lines is applied to each of the boost capacitors and each of the stabilization capacitors.

9. A semiconductor device including a plurality of capacitors, the semiconductor device comprising:

first to (N+1)th power supply lines (N is an integer greater than two);

first to 2N-th switching elements, one end of the first switching element being connected with the first power supply line, one end of the 2N-th switching element being connected with the (N+1)th power supply line, and the switching elements other than the first and 2N-th switching elements being connected in series between the other end of the first switching element and the other end of the 2N-th switching element;

first to (N−1)th boost capacitors, one end of each of the boost capacitors being connected with a j-th connection node (1≦j≦2N−3, j is an odd number) to which the j-th and (j+1)th switching elements are connected, and the other end of the boost capacitor being connected with a (j+2)th connection node to which the (j+2)th and (j+3)th switching elements are connected; and

first to (N−2)th stabilization capacitors, one end of each of the stabilization capacitors being connected with a k-th connection node (2≦k≦2N−4, k is an even number) to which the k-th and (k+1)th switching elements are connected, and the other end of the stabilization capacitor being connected with a (k+2)th connection node to which the (k+2)th and (k+3)th switching elements are connected,

wherein the switching elements are controlled so that one of the m-th switching element (1≦m≦2N−1, m is an integer) and the (m+1)th switching element is turned on.

10. The semiconductor device as defined in claim 9 , further comprising:

an (N−1)th stabilization capacitor connected between the N-th power supply line and the (N+1)th power supply line,

wherein the (N−1)th stabilization capacitor stores an electric charge discharged from the (N−1)th boost capacitor in the second period.

11. The semiconductor device as defined in claim 9 , comprising:

first and second terminals electrically connected with the first and (N+1)th power supply lines, respectively,

wherein a capacitor is connected between the first terminal and the second terminal outside the semiconductor device.

12. The semiconductor device as defined in claim 9 , comprising:

a voltage regulation circuit which regulates voltage,

wherein voltage regulated by the voltage regulation circuit is supplied as a voltage between the first and second power supply lines.

13. The semiconductor device as defined in claim 12 , wherein the voltage regulation circuit regulates voltage based on a comparison result between a reference voltage and a voltage between the first and (N+1)th power supply lines or a comparison result between the reference voltage and a divided voltage obtained by dividing the voltage between the first and (N+1)th power supply lines.

14. The semiconductor device as defined in claim 9 , comprising a voltage regulation circuit which changes frequencies of switch control signals based on a comparison result between a reference voltage and a divided voltage obtained by dividing a voltage between the first and (N+1)th power supply lines, the switch control signals being used for controlling the first to 2N-th switching elements to be turned on and off.

15. The semiconductor device as defined in claim 9 , comprising a multi-valued voltage generation circuit which generates multi-valued voltages based on a voltage between the first and (N+1)th power supply lines.

16. The semiconductor device as defined in claim 15 , comprising a driver section which drives an electro-optical device based on the multi-valued voltages generated by the multi-valued voltage generation circuit.

17. The semiconductor device as defined in claim 9 , wherein the voltage between the first and second power supply lines is applied to each of the boost capacitors and each of the stabilization capacitors.

18. A display device, comprising:

a plurality of scan lines;

a plurality of data lines;

a plurality of pixels;

a scan driver which drives the scan lines; and

the semiconductor device as defined in claim 16 which drives the data lines.