IP Library Granted Patent US 7,007,115
Granted Patent B2
US 7,007,115 · App. 10/623,209 · Granted Feb 28, 2006

Removing lane-to-lane skew

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,007,115
App. No.
10/623,209
Granted
Feb 28, 2006
Kind
B2
Abstract

A first serial buffer having a delivering end may deliver first data from a first position. A second serial buffer having a delivering end may deliver second data from a second position. The first position relative to the delivering end of the first serial buffer may be different than the second position relative to the delivering end of the second serial buffer.

Claims (46)

1. A method comprising:

delivering first data from a first position in a first serial buffer having a receiving end to receive the first data and a delivering end opposite the receiving end; and

delivering second data from a second position in a second serial buffer having a receiving end to receive the second data and a delivering end opposite the receiving end, and the first position relative to the delivering end of the first serial buffer is different than the second position relative to the delivering end of the second serial buffer.

2. The method of claim 1 including delivering the first data from the first position in the first serial buffer having a number of elements that exceeds a maximum lane-to-lane skew.

3. The method of claim 2 including delivering the first data from the first position in the first serial buffer having eight elements.

4. The method of claim 1 further including locating a first element in the first serial buffer and thereafter allowing X=B*E bits to proceed through the first serial buffer before delivering the first data, wherein B equals a number of bits capable of being stored in an element, and E equals a number of elements in the first serial buffer.

5. The method of claim 1 further including determining a location of a first element in the first serial buffer, basing the first position on the location of the first element in the first serial buffer, determining a location of a second element in the second serial buffer, and basing the second position on the location of the second element in the second serial buffer.

6. The method of claim 1 further including locating a first element in the first serial buffer, and locating a second element in the second serial buffer, independently.

7. An article comprising a medium storing instructions that, if executed, enable a processor-based system to:

deliver first data from a first position in a first serial buffer having a receiving end to receive the first data and a delivering end opposite the receiving end; and

deliver second data from a second position in a second serial buffer having a receiving end to receive the second data and a delivering end opposite the receiving end, and the first position relative to the delivering end of the first serial buffer is different than the second position relative to the delivering end of the second serial buffer.

8. The article of claim 7 storing instructions that, if executed, enable a processor-based system to deliver the first data from the first position in the first serial buffer having a number of elements that exceeds a maximum lane-to-lane skew.

9. The article of claim 8 storing instructions that, if executed, enable a processor-based system to deliver the first data from the first position in the first serial buffer having eight elements.

10. The article of claim 7 further storing instructions that, if executed, enable a processor-based system to locate a first element in the first serial buffer and thereafter allow X=B*E bits to proceed through the first serial buffer before delivering the first data, wherein B equals a number of bits capable of being stored in an element, and E equals a number of elements in the first serial buffer.

11. The article of claim 7 further storing instructions that, if executed, enable a processor-based system to:

determine a location of a first element in the first serial buffer; and

determine a location of a second element in the second serial buffer, and the first position is based on the location of the first element in the first serial buffer, and the second position is based on the location of the second element in the second serial buffer.

12. The article of claim 7 further storing instructions that, if executed, enable a processor-based system to:

locate a first element in the first serial buffer; and

locate a second element in the second serial buffer, wherein locating the first element and locating the second element are capable of being performed independently.

13. An apparatus comprising:

a first serial buffer to receive first data at a receiving end of the first serial buffer, and the first serial buffer includes a delivering end, opposite the receiving end, and a first position;

a second serial buffer to receive second data at a receiving end of the second serial buffer, and the second serial buffer includes a delivering end, opposite the receiving end, and a second position; and

a controller to determine that the first data is to be delivered from the first position and that the second data is to be delivered from the second position, and the first position relative to the delivering end of the first serial buffer is different than the second position relative to the delivering end of the second serial buffer.

14. The apparatus of claim 13 , wherein the first serial buffer includes a number of elements, and the number of elements exceeds a maximum lane-to-lane skew.

15. The apparatus of claim 14 , wherein the number of elements is eight.

16. The apparatus of claim 13 including the controller to locate a first element in the first serial buffer and to allow X=B*E bits to proceed through the first serial buffer after the first element is located before delivering the first data, wherein B equals a number of bits capable of being stored in an element, and E equals a number of elements in the first serial buffer.

17. The apparatus of claim 13 including the controller to determine a location of a first element in the first serial buffer and to determine a location of a second element in the second serial buffer, and the first position is based on the location of the first element in the first serial buffer, and the second position is based on the location of the second element in the second serial buffer.

18. The apparatus of claim 13 including the controller to locate a first element in the first serial buffer and to locate a second element in the second serial buffer, and locating the first element and locating the second element are capable of being performed independently.

19. The apparatus of claim 13 , wherein the apparatus is an Ethernet controller.

20. The apparatus of claim 13 , wherein the apparatus is an InfiniBand™ adaptor.

21. A system comprising:

a processor-based device;

a bridge to direct data received from the processor-based device; and

a storage coupled to the processor-based device storing instructions that, if executed, enable the processor-based device to:

deliver first data from a first position in a first serial buffer having a receiving end to receive the first data and a delivering end opposite the receiving end, and

deliver second data from a second position in a second serial buffer having a receiving end to receive the second data and a delivering end opposite the receiving end, and the first position relative to the delivering end of the first serial buffer is different than the second position relative to the delivering end of the second serial buffer.

22. The system of claim 21 storing instructions that, if executed, enable the processor-based device to deliver the first data from the first position in the first serial buffer having a number of elements that exceeds a maximum lane-to-lane skew.

23. The system of claim 22 storing instructions that, if executed, enable the processor-based device to deliver the first data from the first position in the first serial buffer having eight elements.

24. The system of claim 21 further storing instructions that, if executed, enable the processor-based device to locate a first element in the first serial buffer and thereafter allow X=B*E bits to proceed through the first serial buffer before delivering the first data, wherein B equals a number of bits capable of being stored in an element, and E equals a number of elements in the first serial buffer.

25. The system of claim 21 further storing instructions that, if executed, enable the processor-based device to:

determine a location of a first element in the first serial buffer; and

determine a location of a second element in the second serial buffer, and the first position is based on the location of the first element in the first serial buffer, and the second position is based on the location of the second element in the second serial buffer.

26. The system of claim 21 further storing instructions that, if executed, enable the processor-based device to:

locate a first element in the first serial buffer; and

locate a second element in the second serial buffer, wherein locating the first element and locating the second element are capable of being performed independently.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2003
From: ELBOIM, YARON; WIENER, AMIR
To: INTEL CORPORATION
Reel/Frame 014317/0859 →
Continuity (1)
Related Publication 20050015522A1 · Jan 20, 2005