Transistor with strain-inducing structure in channel
Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
1. An apparatus comprising:
a substrate comprising a first lattice structure;
a strain-inducing layer disposed on the substrate having a second lattice structure different than the first lattice structure; and
a strained layer disposed on the strain-inducing layer,
wherein the strain-inducing layer and the strained layer are disposed in a channel region for a transistor device and the second lattice structure is defined by a lateral contraction or expansion of the strain-inducing layer,
wherein when the strain-inducing layer comprises silicon germanium,
germanium comprises between approximately 20 and 25 percent of the silicon germanium.
2. The apparatus of claim 1 , further comprising:
a gate electrode disposed on the strained layer;
a first spacer disposed adjacent to a first side of the gate electrode; and
a second spacer disposed adjacent to a second side of the gate electrode,
wherein the stain-inducing layer and the strained layer comprises lateral edges defined by an edge of the first spacer and an edge of the second spacer.
3. The apparatus of claim 1 , wherein the apparatus comprises:
an n-type metal oxide semiconductor.
4. The apparatus of claim 3 , wherein the strain-inducing layer comprises:
silicon germanium.
5. The apparatus of claim 4 , wherein the silicon germanium layer has a thickness of between approximately 400 and 500 Å.
6. The apparatus of claim 5 , wherein the strained layer comprises silicon and has a thickness of between approximately 100 and 200 Å.
7. The apparatus of claim 1 , wherein the apparatus comprises:
a p-type metal oxide semiconductor.
8. The apparatus of claim 7 , wherein the strain-inducing layer comprises:
silicon carbide.
9. The apparatus of claim 8 , wherein carbon comprises between approximately 1 and 2 percent of the silicon carbide.
10. A system comprising:
an integrated circuit package comprising
a substrate comprising a first lattice structure,
a strain-inducing layer disposed on the substrate, the strain-inducing layer comprising a second lattice structure different than the first lattice structure, and
a strained layer disposed on the strain-inducing layer,
wherein the strain-inducing layer and the strained layer are disposed in a channel region for a transistor device and the second lattice structure is defined by a lateral contraction or expansion of the strain-inducing layer,
wherein when the strain-inducing layer comprises silicon germanium,
germanium comprises between approximately 20 and 25 percent of the silicon germanium.
11. The system of claim 10 , wherein the system comprises:
an n-type metal oxide semiconductor.
12. The system of claim 11 , wherein the strain-inducing layer comprises:
silicon germanium.
13. The system of claim 10 , wherein the system comprises:
a p-type metal oxide semiconductor.
14. The system of claim 13 , wherein the strain-inducing layer comprises:
silicon carbide.
15. The system of claim 14 , wherein carbon comprises between approximately 1 and 2 percent of the silicon carbide.