Parallel compression test circuit of memory device
A parallel compression test circuit of a memory device operates write drivers sequentially in a parallel compression test to disperse peak current and reduce noise. The circuit comprises a write driving control unit for generating a plurality of write driving control signals in response to a column operation pulse signal at the same timing in a normal mode, at a different timing in the parallel compression test mode.
1. A parallel compression test circuit of a memory device, comprising:
a plurality of banks each comprising a plurality of bit line sense amplifiers for sensing and amplifying data on a bit line;
a plurality of driving units for driving data on a global input/output line in response to a plurality of write driving control signals to transmit the data to the bit line sense amplifier;
a plurality of global input/output write driving units for driving inputted data to transmit the data to the global input/output line; and
a write driving control unit for generating the plurality of write driving control signals in response to a column operation pulse signal, wherein the plurality of write driving control signals are generated at the same timing in a normal mode and at a different timing in a parallel compression test mode.
2. The parallel compression test circuit according to claim 1 , wherein the write driving control unit comprises:
a plurality of first delay units for sequentially delaying the column operation pulse signal; and
a plurality of write driving control signal generating units for generating the plurality of write driving control signals with output signals from the plurality of first delay units in response to a parallel compression test mode signal.
3. The parallel compression test circuit according to claim 2 , wherein the plurality of first delay units have the same delay time.
4. The parallel compression test circuit according to claim 2 , wherein the write driving control unit comprises a normal mode control unit for controlling the plurality of write driving control signals to be generated at the same timing in response to the parallel compression test mode signal in the normal mode.
5. The parallel compression test circuit according to claim 1 , wherein the write driving control unit comprises:
a second delay unit for delaying the column operation pulse signal at a different delay time; and
a plurality of write driving control signal generating units for generating the plurality of write driving control signals with output signals from the plurality of second delay units in response to a parallel compression test mode signal.
6. The parallel compression test circuit according to claim 5 , wherein the write driving control unit comprises a normal mode control unit for controlling the plurality of write driving control signals to be generated at the same timing in response to the parallel compression test mode signal in the normal mode.