High bandwidth datapath load and test of multi-level memory cells
An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.
1. An article comprising a storage medium storing instructions readable by a processor-based system that, if executed by a processor enables the processor to:
obtain first data;
obtain second data from the multilevel cell memory different from said first data, wherein said first data and said second data include a plurality of bits;
compare said first data with said second data;
wherein the processor programs the multilevel cell memory by executing instructions that enables the processor to:
access a plurality of memory cells in the multilevel cell memory;
determine a number of bits from said memory cells of said first data that need programming; and
enable loading of said first data in the plurality of memory cells based, at least in part, on the determined number of bits from said memory cells of said first data.
2. The article of claim 1 , comprising a storage medium storing instructions readable by a processor-based system that, if executed by a processor enables the processor to:
verify the levels to which said all of the bits in said second data are programmed at substantially the same bandwidth as programming the number of bits per memory cell of said first data.
3. The article of claim 1 , comprising a storage medium storing instructions readable by a processor-based system that, if executed by a processor enables the processor to:
program fewer bits per memory cell of said first data than said all of the number of bits available per memory cell of said first data.
4. The article of claim 1 , comprising a storage medium storing instructions readable by a processor-based system that, if executed by a processor enables the processor to:
store said first data in a data buffer.
5. An article comprising a medium storing instructions readable by a processor-based system that, if executed by a processor enables the processor to:
program a multilevel cell memory based, at least in part, on a comparison of a first data and a second data; and
verify the levels to which said all of the bits in said second data are programmed at substantially the same bandwidth as programming the number of bits per memory cell of said first data.
6. The article of claim 5 , comprising a storage medium storing instructions readable by a processor-based system that, if executed by a processor enables the processor to:
access a plurality of memory cells in the multilevel cell memory; and
determine a number of bits from said memory cells of said first data that need programming.
7. The article of claim 6 , comprising a storage medium storing instructions readable by a processor-based system that, if executed by a processor enables the processor to:
program fewer bits per memory cell of said first data than said all of the number of bits available per memory cell of said first data.
8. The article of claim 6 , comprising a storage medium storing instructions readable by a processor-based system that, if executed by a processor enables the processor to:
store first data in a data buffer.