Method for controlling accuracy and repeatability of an etch process
Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.
1. A method for controlling accuracy and repeatability of an etch process, comprising:
(a) providing a batch of substrates, each substrate having a patterned mask formed on a film stack comprising at least one material layer;
(b) measuring dimensions of elements of the patterned mask on at least one substrate of the batch of substrates;
(c) trimming the patterned mask on the at least one substrate using a process recipe based on the measurements performed at step (b), then;
(d) etching the at least one material layer on the at least one substrate;
(e) measuring a thickness of post-etch residue and at least one of compacting or removing at least a portion of the post-etch residue formed on sidewalls of the etched structures based on the thickness of the post-etch residue;
(f) measuring dimensions of etched structures formed on the at least one substrate during step (d); and
(g) adjusting the process recipe of step (c) or/and the process recipe of step (d); based on the measurements performed at step (f).
2. The method of claim 1 wherein the steps (b) and (f) use an optical measuring technique.
3. The method of claim 2 wherein the optical measuring technique is a scatterometric measuring technique.
4. The method of claim 1 wherein the steps (b) through (f) are performed using processing modules of a single substrate processing system.
5. The method of claim 1 wherein the step (g) further comprises:
modifying a time duration or process parameters for trimming the patterned mask.
6. The method of claim 1 wherein the step (g) further comprises:
modifying a time duration or process parameters for etching the material layer.
7. The method of claim 1 further comprising:
thinning the post-etch residue to a thickness of less than about 10 nm.
8. A method for controlling accuracy and repeatability during formation of a gate structure of a field effect transistor, comprising:
(a) providing a batch of substrates, each substrate having a patterned mask formed on a gate electrode layer of the gate structure;
(b) measuring dimensions of elements of the patterned mask on at least one substrate of the batch of substrates;
(c) trimming the patterned mask on the at least one substrate using a process recipe based on the measurements performed at step (b), then;
(d) etching the gate electrode layer on the at least one substrate;
(e) measuring a thickness of post-etch residue and at least one of compacting or removing at least the portion of post-etch residue formed on sidewalls of the etched structures based on the thickness of the post-etch residue;
(f) measuring dimensions of etched gate electrode structures formed on the at least one substrate during step (d); and
(g) adjusting the process recipe of step (c) or/and the process recipe of step (d) based on the measurements performed at step (f).
9. The method of claim 8 wherein the steps (b) and (f) use an optical measuring technique.
10. The method of claim 9 wherein the optical measuring technique is a scatterometric measuring technique.
11. The method of claim 8 wherein the steps (b) through (f) are performed using processing modules of a single substrate processing system.
12. The method of claim 8 wherein the step (g) further comprises:
modifying a time duration or process parameters for trimming the patterned mask.
13. The method of claim 8 wherein the step (g) further comprises:
modifying a time duration or process parameters for etching the material layer.
14. The method of claim 8 wherein the gate electrode layer comprises doped polysilicon.
15. The method of claim 8 wherein the step (d) further comprises:
providing HBr and Cl 2 at a flow ratio HBr:Cl 2 in a range from 1:15 to 15:1.
16. The method of claim 8 further comprising: thinning the post-etch residue to a thickness of less than about 10 nm.
17. The method of claim 15 further comprising:
using a plasma comprising one or more gases selected from the group consisting of nitrogen (N 2 ), oxygen (O 2 ) and hydrogen (H 2 ).
18. The method of claim 17 further comprising:
providing nitrogen (N 2 ) and hydrogen (H 2 ) at a N 2 :H 2 flow ratio in a range from 3:1 to 100% of N 2 ;
maintaining the substrate at a temperature between about 200 and 350 degrees Celsius;
applying power to an inductively coupled power source between about 1000 and 7000 W; and
maintaining a chamber pressure between about 500 and 2000 mTorr.
19. The method of claim 1 , wherein the step (e) further comprises:
measuring a critical dimension of a feature is done in addition to measuring the thickness of the post-etch residue.
20. The method of claim 8 , wherein the step (e) further comprises:
measuring a critical dimension of a feature is done in addition to measuring the thickness of the post-etch residue.