IP Library Granted Patent US 7,166,853
Granted Patent B2
US 7,166,853 · App. 10/241,307 · Granted Jan 23, 2007

Active method and system of establishing electrical contact

Assignee: Varian Semiconductor Equipment Associates, Inc.
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Quick Facts
Patent No.
US 7,166,853
App. No.
10/241,307
Granted
Jan 23, 2007
Kind
B2
Abstract

A system for electrically contacting a semiconductor wafer during implanting of the wafer includes one or more pairs of closely spaced contacts located adjacent the semiconductor wafer and a driving circuit connected to the contacts to provide a discharge from one contact to the semiconductor wafer and from the semiconductor wafer to the other contact of each pair of contacts. The contacts can be spaced apart from the wafer and the tips of the contacts closest to the wafer may have sharp points to aid in the establishment of corona at lower drive voltages. Alternately, the contacts may be rounded and may contact the wafer. The driving circuit may be adapted from a pulsed discharge circuit, such as a Kettering ignition circuit, a capacitance discharge ignition circuit, or a blocking oscillator circuit. Alternately, the driving circuit may be adapted from a continuous discharge circuit, such as a Tesla coil circuit.

Claims (46)

1. A system for making electrical contact to a semiconductor wafer for implanting of the wafer, comprising:

at least one pair of closely spaced contacts located adjacent the semiconductor wafer;

a driving circuit connected to the contacts to provide a discharge from a first contact of each pair of contacts to the semiconductor wafer and from the semiconductor wafer to the other contact of each pair of contacts.

2. The system of claim 1 , wherein the contacts terminate in sharp points adjacent the semiconductor wafer.

3. The system of claim 1 , wherein the contacts terminate in rounded tips adjacent the semiconductor wafer.

4. The system of claim 3 , wherein the contacts contact an insulating surface coating on the semiconductor wafer, the discharge passing through the insulating surface coating to a conductive interior portion of the semiconductor wafer.

5. The system of claim 4 , wherein the driving circuit comprises:

a transformer having a primary winding and a balanced secondary winding, the contacts being driven from the balanced secondary winding; and

a center tap on the secondary winding, the center tap tied to a chosen potential.

6. The system of claim 5 , wherein the driving circuit is gated to correspond the discharge with deposition pulses of a pulsed plasma deposition implantation process.

7. The system of claim 1 , wherein the contacts comprise:

a center conductor of a coaxial cable; and

an outer, grounded conductor of the coaxial cable.

8. The system of claim 1 , wherein a gap distance between the contacts and the semiconductor wafer is less than a least separation distance between the contacts.

9. The system of claim 8 , wherein the contacts are fabricated of refractory metal.

10. The system of claim 8 , wherein the driving circuit comprises:

a transformer having a primary winding and a balanced secondary winding, the contacts being driven from the balanced secondary winding; and

a center tap on the secondary winding, the center tap tied to a chosen potential.

11. The system of claim 10 , wherein the driving circuit is gated to correspond the discharge with deposition pulses of a pulsed plasma deposition implantation process.

12. The system of claim 11 , wherein the driving circuit is controlled to provide gating between at least two of the discharge types contained in the list including corona discharge, glow discharge, arc discharge and spark discharge.

13. The system of claim 1 , wherein the contacts are fabricated of refractory metal.

14. The system of claim 1 , wherein the driving circuit comprises:

a transformer having a primary winding and a balanced secondary winding, the contacts being driven from the balanced secondary winding; and

a center tap on the secondary winding, the center tap tied to a chosen potential.

15. The system of claim 14 , wherein the driving circuit is chosen from a group of circuits including Kettering ignition circuits, capacitive discharge ignition circuits, Tesla coil circuits and blocking oscillator, circuits.

16. The system of claim 15 , wherein the driving circuit is a Tesla coil circuit having at least one RF amplifier/oscillator.

17. The system of claim 15 , wherein the driving circuit is a Tesla coil circuit having at least one of the primary winding and the secondary winding being resonated.

18. The system of claim 1 , wherein the driving circuit is chosen from a group of circuits including Kettering ignition circuits, capacitive discharge ignition circuits, Tesla coil circuits and blocking oscillator circuits.

19. The system of claim 18 , wherein the driving circuit is a Tesla coil circuit having at least one RF amplifier/oscillator.

20. The system of claim 18 , wherein the driving circuit is a Tesla coil circuit having at least one of the primary winding and the secondary winding being resonated.

21. The system of claim 1 , wherein the driving circuit is gated to correspond the discharge with deposition pulses of a pulsed plasma deposition implantation process.

22. The system of claim 21 , wherein:

leading edges of the deposition pulses trail corresponding leading edges of the discharge; and

trailing edges of the deposition pulses do not trail corresponding trailing edges of the discharge.

23. The system of claim 22 , the driving circuit is controlled to provide gating between at least two of the discharge types contained in the list including corona discharge, glow discharge, arc discharge and spark discharge.

24. A circuit for electrically contacting a semiconductor wafer in conjunction with implantation of the semiconductor wafer by the pulsed plasma deposition method, the circuit comprising:

a transformer having a primary winding and a balanced secondary winding;

a center tap on the secondary winding, the center tap tied to a chosen potential;

a pair of spaced apart contacts being driven from the balanced secondary winding and being located adjacent the semiconductor wafer, the circuit providing a discharge from one contact of the pair of contacts to the semiconductor wafer and from the semiconductor wafer to the other contact of the pair of contacts; and

gating means to correspond the discharge with deposition pulses of the pulsed plasma deposition method.

25. The circuit of claim 24 , wherein the gating means controls the discharge between at least two of the discharge types contained in the list including corona discharge, glow discharge, arc discharge and spark discharge.

26. The circuit of claim 24 , wherein the circuit is chosen from a group of pulsed discharge circuits including capacitive discharge ignition circuits and blocking oscillator circuits.

27. The system of claim 26 , wherein the contacts contact an insulating surface coating on the semiconductor wafer, the discharge passing through the insulating surface coating to a conductive interior portion of the semiconductor wafer.

28. A method of electrically contacting a semiconductor wafer for implantation of the semiconductor wafer, comprising energizing a circuit to create a discharge between a pair of contacts adjacent an insulating surface layer of the semiconductor wafer, wherein the discharge results in electrical breakdown of the insulating surface layer to form a conductive pathway from one of the contacts, through the insulating surface layer, to a conductive interior portion of the semiconductor wafer and from the conductive interior portion, through the insulating surface layer, to the other of the contacts.

29. The method of claim 28 , comprising gating the discharge to correspond the discharge with deposition pulses of a pulsed plasma deposition implantation process.

30. The method of claim 29 , wherein the gating comprises controlling the discharge to provide gating between at least two of the discharge types contained in the list including corona discharge, glow discharge, arc discharge and spark discharge.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2002
From: RHOADS, KEVIN G.
To: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
Reel/Frame 013287/0322 →
Continuity (1)
Related Publication 20040046539A1 · Mar 11, 2004