Double gate (DG) SOI ratioed logic with intrinsically on symmetric DG-MOSFET load
View Patent ↗Disclosed is a Silicon-On-Insulator (SOI) Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) logic family composed of ratioed logic with intrinsically “on” symmetric fully depleted double-gate (DG) SOI MOSFET load(s) and asymmetric fully depleted double gate MOSFET driver(s).
1. An SOI MOSFET inverter comprising:
a) a multitude of terminals including:
i) an input terminal;
ii) an output terminal;
iii) a supply voltage terminal; and
iv) a ground terminal;
b) an SDG load structure including:
i) a first SDG junction having an n+ area connected to said supply voltage terminal;
ii) a second SDG junction having an n+ area connected to said output terminal;
iii) a first SDG gate having an n+ polysilicon area connected to said output terminal; and
iv) a second SDG gate having an n+ polysilicon area connected to said output terminal; and
c) an ADG load structure including:
i) a first ADG junction having an n+ area connected to said ground terminal;
ii) a second ADG junction having an n+ area connected to said output terminal;
iii) a first ADG gate having an n+ polysilicon area connected to said input terminal; and
iv) a second ADG gate having an p+ polysilicon area connected to said input terminal.
2. A system according to claim 1 , wherein said SDG load structure and said ADG load structure are constructed to satisfy an SDG load inverter ratio.
3. A system according to claim 1 , further including a load capacitor connected between said ground terminal and said output terminal.
4. A system according to claim 1 , wherein said ADG driver structure and said SDG load structure are fabricated on the same substrate.
5. A system according to claim 1 , wherein said ADG driver structure and said SDG load structure have buried gates.
6. A system according to claim 1 , wherein said ADG driver structure and said SDG load structure are fabricated using a dual poly process.
7. A two input SOI MOSFET NOR circuit comprising:
a) a multitude of terminals including:
i) a first input terminal;
ii) a second input terminal;
iii) an output terminal;
iv) a supply voltage terminal; and
v) a ground terminal;
b) an SDG load structure including:
i) a first SDG junction having an n+ area connected to said supply voltage terminal;
ii) a second SDG junction having an n+ area connected to said output terminal;
iii) a first SDG gate having an n+ polysilicon area connected to said output terminal; and
iv) a second SDG gate having an n+ polysilicon area connected to said output terminal; and
c) an ADG load structure including:
i) a first ADG junction having an n+ area connected to said ground terminal;
ii) a second ADG junction having an n+ area connected to said output terminal;
iii) a first ADG gate having an n+ polysilicon area connected to said input1 terminal; and
iv) a second ADG gate having an p+ polysilicon area connected to said input2 terminal.
8. A system according to claim 7 , wherein said SDG load structure and said ADG load structure are constructed to satisfy an SDG load inverter ratio.
9. A system according to claim 7 , further including a load capacitor connected between said ground terminal and said output terminal.
10. A system according to claim 7 , wherein said ADG driver structure and said SDG load structure are fabricated on the same substrate.
11. A system according to claim 7 , wherein said ADG driver structure and said SDG load structure have buried gates.
12. A system according to claim 7 , wherein said ADG driver structure and said SDG load structure are fabricated using a dual poly process.
13. An n input SOI MOSFET NOR circuit comprising:
a) a multitude of terminals including:
i) n input terminals;
ii) an output terminal;
iii) a supply voltage terminal; and
iv) a ground terminal;
b) an SDG load structure including:
i) a first SDG junction having an n+ area connected to said supply voltage terminal;
ii) a second SDG junction having an n+ area connected to said output terminal;
iii) a first SDG gate having an n+ polysilicon area connected to said output terminal; and
iv) a second SDG gate having an n+ polysilicon area connected to said output terminal; and
c) n/2 ADG load structures, each of said ADG load structures including:
i) a first ADG junction having an n+ area connected to said ground terminal;
ii) a second ADG junction having an n+ area connected to said output terminal;
iii) a first ADG gate having an n+ polysilicon area connected to one of said input terminals; and
iv) a second ADG gate having an p+ polysilicon area connected to another of said input terminals.
14. A system according to claim 13 , wherein said SDG load structure and at least one of said n/2 ADG load structures are constructed to satisfy an SDG load inverter ratio.
15. A system according to claim 13 , further including a load capacitor connected between said ground terminal and said output terminal.
16. A system according to claim 13 , wherein said n/2 ADG driver structures and said SDG load structure are fabricated on the same substrate.
17. A system according to claim 13 , wherein said n/2 ADG driver structures and said SDG load structure have buried gates.
18. A system according to claim 13 , wherein said n/2 ADG driver structure and said SDG load structure are fabricated using a dual poly process.
19. An SOI MOSFET NAND gate comprising:
a) a multitude of terminals including:
i) a first input terminal;
ii) a second input terminal;
iii) an output terminal;
iv) a supply voltage terminal; and
v) a ground terminal;
b) an ADG load structure including:
i) a first ADG junction having a p+ area connected to said supply voltage terminal;
ii) a second ADG junction having a p+ area connected to said output terminal;
iii) a first ADG gate having a p+ polysilicon area connected to said first input terminal; and
iv) a second SDG gate having an n+ polysilicon area connected to said second input terminal; and
c) an SDG load structure including:
i) a first SDG junction having an n+ area connected to said ground terminal;
ii) a second SDG junction having an n+ area connected to said output terminal;
iii) a first SDG gate having an n+ polysilicon area connected to said ground terminal; and
iv) a second SDG gate having an n+ polysilicon area connected to said ground terminal.
20. An SOI MOSFET NAND gate comprising:
a) a multitude of terminals including:
i) a first input terminal;
ii) a second input terminal;
iii) an output terminal;
iv) a supply voltage terminal; and
v) a ground terminal;
b) an SDG load structure including:
i) a first SDG junction having an n+ area connected to said supply voltage terminal;
ii) a second SDG junction having an n+ area connected to said output terminal;
iii) a first SDG gate having an n+ polysilicon area connected to said output terminal; and
iv) a second SDG gate having an n+ polysilicon area connected to said output terminal;
c) a first ADG load structure including:
i) a first ADG junction having an n+ area connected to said second SDG terminal;
ii) a second ADG junction having an n+ area connected to said first input terminal;
iii) a first ADG gate having an n+ polysilicon area connected to said first input terminal; and
iv) a second ADG gate having an p+ polysilicon area connected to said first input terminal; and
d) a second ADG load structure including:
i) a third ADG junction having an n+ area connected to said first input terminal;
ii) a fourth ADG junction having an n+ area connected to said ground terminal;
iii) a third ADG gate having an n+ polysilicon area connected to said second input terminal; and
iv) a fourth ADG gate having an p+ polysilicon area connected to said second input terminal.
21. An SOI MOSFET XOR gate comprising:
a) a multitude of terminals including:
i) a first input terminal;
ii) a first bar input terminal;
iii) a second input terminal;
iv) a second bar input terminal;
v) an output terminal;
vi) a supply voltage terminal; and
vii) a ground terminal;
b) an SDG load structure including:
i) a first SDG junction having an n+ area connected to said supply voltage terminal;
ii) a second SDG junction having an n+ area connected to said output terminal;
iii) a first SDG gate having an n+ polysilicon area connected to said output terminal; and
iv) a second SDG gate having an n+ polysilicon area connected to said output terminal;
c) a first ADG load structure including:
i) a first ADG junction having an n+ area connected to said second SDG terminal;
ii) a second ADG junction having an n+ area;
iii) a first ADG gate having an n+ polysilicon area connected to said first input terminal; and
iv) a second ADG gate having an p+ polysilicon area connected to said second bar input terminal; and
d) a second ADG load structure including:
i) a third ADG junction having an n+ area connected to said second ADG junction;
ii) a fourth ADG junction having an n+ area connected to said ground terminal;
iii) a third ADG gate having an n+ polysilicon area connected to said first bar input terminal; and
iv) a fourth ADG gate having an p+ polysilicon area connected to said second input terminal.