IP Library Granted Patent US 7,183,621
Granted Patent B2
US 7,183,621 · App. 10/761,247 · Granted Feb 27, 2007

MRAM memory cell having an electroplated bottom layer

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Quick Facts
Patent No.
US 7,183,621
App. No.
10/761,247
Granted
Feb 27, 2007
Kind
B2
Abstract

The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

Claims (36)

1. A magnetic random access memory structure comprising:

a longitudinally extending planarized conductive line formed within an insulating layer;

an electroplated bottom sense layer extending longitudinally over said conductive line;

a nonmagnetic tunnel barrier layer over said sense layer;

a pinned layer over said nonmagnetic layer; and

at least one electrical conductor in contact with said pinned layer.

2. The structure of claim 1 wherein said sense layer is formed of NiFe.

3. The structure of claim 1 wherein said insulating layer is selected from the group consisting of BPSG, SiO, SiO 2 , Si 3 N 4 and polyimide.

4. The structure of claim 1 wherein said nonmagnetic layer is aluminum oxide.

5. The structure of claim 1 wherein said sense layer is a ferromagnetic sense layer.

6. The structure of claim 1 wherein said pinned layer is formed of a plurality of layers to produce a ferromagnetic pinned layer.

7. A processor-based system, comprising:

a processor; and

an integrated circuit coupled to said processor, said integrated circuit including a plurality of magnetic random access memory cells, each of said magnetic random access memory cells including an electroplated bottom sense layer formed over a planarized conductor, the bottom sense layer extending longitudinally over said planarized conductor, a nonmagnetic layer formed over said sense layer and a pinned layer formed over said nonmagnetic layer.

8. The system of claim 7 wherein said sense layer is formed of NiFe.

9. The system of claim 7 wherein said nonmagnetic layer is aluminum oxide.

10. The system of claim 7 wherein said sense layer is a ferromagnetic sense layer.

11. The system of claim 7 wherein said pinned layer is formed of a plurality of layers to produce a ferromagnetic pinned layer.

12. A magnetic random access memory structure comprising:

a longitudinally extending planarized conductive line formed within an insulating layer;

an electroplated ferromagnetic layer extending longitudinally over said conductive line;

a nonmagnetic tunnel barrier layer over said electroplated ferromagnetic layer;

an upper ferromagnetic layer over said nonmagnetic layer; and

at least one electrical conductor in contact with said upper layer.

13. The structure of claim 12 wherein said electroplated ferromagnetic layer is formed of NiFe.

14. The structure of claim 12 wherein said insulating layer is selected from the group consisting of BPSG, SiO, SiO 2 , Si 3 N 4 and polyimide.

15. The structure of claim 12 wherein said nonmagnetic layer is aluminum oxide.

16. The structure of claim 12 wherein said electroplated ferromagnetic layer is a ferromagnetic sense layer.

17. The structure of claim 12 , wherein said upper layer is formed of a plurality of layers to produce a ferromagnetic pinned layer.

18. A processor-based system, comprising:

a processor; and

an integrated circuit coupled to said processor, said integrated circuit including a plurality of magnetic random access memory cells, each of said magnetic random access memory cells including an electroplated bottom sense layer formed over a planarized conductor, the bottom sense layer extending longitudinally over said planarized conductor, a nonmagnetic layer formed over said sense layer and a pinned layer formed over said nonmagnetic layer.

19. The system of claim 18 wherein said sense layer is formed of NiFe.

20. The system of claim 18 wherein said nonmagnetic layer is aluminum oxide.

21. The system of claim 18 wherein said sense layer is a ferromagnetic sense layer.

22. The system of claim 18 wherein said pinned layer is formed of a plurality of layers to produce a ferromagnetic pinned layer.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →