Ferroelectric memory transistor with highly-oriented film on gate insulator
A method for fabricating a non-volatile memory device. The method includes providing a substrate, e.g., silicon. The method also includes forming an oxide layer overlying the substrate; and forming a buffer layer overlying the oxide layer. A ferroelectric material is formed overlying the substrate and is formed preferably overlying the buffer layer. The method also includes forming a gate layer overlying the ferroelectric material, where the gate layer is overlying a channel region. The method further includes forming first source/drain region adjacent to a first side of the channel region and a second source/drain region adjacent to a second side of the channel region. In other embodiments, the method can also include other steps.
1. A non-volatile memory device, comprising:
a p-type substrate;
an oxide layer overlying the substrate;
a buffer layer overlying the oxide layer that is highly-oriented and has a crystalline structure;
a ferroelectric material formed on the buffer layer, the ferroelectric layer being highly-oriented;
a gate electrode overlying the ferroelectric material, the gate electrode overlying a channel region; and
a first source/drain region adjacent to a first side of the channel region and a second source/drain region adjacent to a second side of the channel region,
wherein the buffer layer is a MgO layer that has been formed on the oxide layer to a thickness of less than 10 nm using a sputtering method.
2. The non-volatile memory device of claim 1 , wherein the buffer layer has a polycrystalline structure.
3. The non-volatile memory device of claim 1 , wherein the ferroelectric material is highly oriented.
4. The non-volatile memory device of claim 1 , wherein the oxide layer is provided by a dry oxidation process comprising an oxygen bearing compound.
5. The non-volatile memory device of claim 1 , wherein the buffer layer is thermally annealed to enhance an alignment of crystallites of the MgO layer.
6. The non-volatile memory device of claim 5 wherein the buffer layer is thermally annealed at a temperature of 800–1000 degrees Celsius.
7. The non-volatile memory device of claim 1 wherein the ferroelectric material is a PZT bearing compound, wherein the thickness of the buffer layer is 7 nm.
8. The non-volatile memory device of claim 7 , wherein the ferroelectric material has a thickness of less than about 1,000 angstroms.
9. The non-volatile memory device of claim 7 , wherein the ferroelectric material has a thickness of about 100 angstroms and greater.