Multi-planar layout vertical thin-film transistor inverter

1. A method for forming a multi-planar layout thin-film transistor (TFT) inverter circuit, the method comprising:

forming a P-channel top drain vertical (TDV)-TFT with a gate having a length, and a width greater than the length, a first source/drain (S/D) region in a first horizontal plane, and a second S/D) region in a second horizontal plane, different than the first horizontal plane, as viewed in a vertical cross-section;

forming an N-channel TDV-TFT, adjacent the P-channel TFT, with a gate having a length, and a width greater than the length, a third S/D region in a third horizontal plane, and a fourth S/D region in the second horizontal plane, different than the third plane

wherein forming P and N-channel TDV-TFTs includes:

forming a P-channel rate connected to a gate contact, having sidewalls and a ton surface, overlying a substrate insulation layer;

forming an N-channel gate connected to the gate contact, having sidewalls and a top surface, overlying the substrate insulation layer;

forming a cap oxide layer overlying the P and N-channel gate top surfaces;

forming a gate oxide layer overlying the P and N-channel gate sidewalls;

forming the first S/D region overlying the P-channel cap oxide layer;

forming the second S/D region overlying the substrate insulation layer, adjacent a P-channel gate first sidewall;

forming a first channel region overlying the P-channel gate first sidewall, interposed between the first and second S/D regions;

forming the third S/D region overlying the N-channel cap oxide layer;

forming the fourth S/D region overlying the substrate insulation layer, adjacent an N-channel gate first sidewall, and connected to the second S/D region;

forming a second channel region overlying the N-channel gate first sidewall, interposed between the third and fourth S/D regions; and,

wherein the N-channel and P-channel and P-channel TDV-TFTs share the second and fourth S/D region.

2. The method of claim 1 wherein forming a P-channel gate includes forming a gate with a first thickness;

wherein forming an N-channel gate includes forming a gate with a second thickness; and,

wherein forming first and second channel regions includes forming first and second channel regions with channel lengths about equal to the first and second thicknesses, respectively.

3. The method of claim 1 further comprising:

following the formation of the cap oxide layer, conformally depositing a silicon (Si) layer; and,

wherein forming the first S/D region, second S/D region, third S/D region, fourth S/D region, first channel region, and second channel region includes forming the regions from the conformally deposited Si layer.

4. The method of claim 3 further comprising:

forming a lightly doped drain (LDD) in the first and second channel regions adjacent the first and third S/D) regions, respectively.

5. The method of claim 3 further comprising:

providing a substrate made from a material selected from group including Si, quartz, glass, and plastic;

conformally depositing a substrate insulation layer overlying the substrate, made from a material selected from the group including SiO2, SiO2/Si3N4/SiO2, and organic insulators such as polyimide; and,

following the formation of the P and N-channel gates, etching the exposed substrate insulation layer.

6. The method of claim 5 wherein forming P and N-channel gates includes forming the gates on a substrate insulation layer having a surface along a fourth plane;

wherein etching the exposed substrate insulation layer includes forming a recess in the substrate insulation layer, lower than the fourth plane; and,

wherein forming first and second channel regions overlying the P and N-channel gate first sidewalls includes extending the channel regions into the substrate insulation layer recess.

7. The method of claim 5 wherein forming P and N-channel gates overlying the substrate insulation layer includes:

depositing a Si layer with first and second thicknesses, and sidewalls, overlying the insulating layer;

P+ doping the first thickness of Si to form the P-channel gate; and,

N+ doping the second thickness of Si to form the N-channel gate.

8. The method of claim 2 wherein forming P and N-channel gates with a first and second thicknesses includes the thicknesses being in the range of 1000 to 6000 Å.

9. The method of claim 7 wherein forming a gate oxide layer overlying the P and N-channel gate sidewalk includes plasma oxidizing the gate Si layer sidewalls; and,

wherein forming a cap oxide layer overlying the P and N-channel gate top surfaces includes forming a cap oxide layer from a material selected from the group including SiO2 and Si3N4, having a thickness in the range of 300 to 1500 Å.

10. The method of claim 5 wherein conformally depositing a Si layer overlying the cap oxide layer includes depositing an amorphous Si layer having a thickness in the range of 300 to 1000 Å;

the method further comprising:

performing a Vt adjust implant in the first and second channel regions; and,

crystallizing the amorphous Si layer.

11. The method of claim 1 further comprising:

depositing a silicide metal selected from the group including Ni, Ti, and Co, overlying the first, second, third, and fourth S/D regions;

annealing to form a metal silicide; and,

removing the unreacted metal.

12. The method of claim 10 further comprising:

depositing an absorption oxide layer overlying the amorphous Si layer, having a thickness in the range of 1000 Å to 1.5 microns; and

wherein crystallizing the amorphous Si layer includes excimer and CO2 laser irradiating the absorption oxide layer, to heat the underlying amorphous Si.

13. The method of claim 10 further comprising:

depositing a screen oxide layer overlying the amorphous Si layer, having a thickness in the range of 300 to 1000 Å;

wherein forming first, second, third, and fourth S/D regions includes performing source/drain implants through the screen oxide layer; and,

the method further comprising:

performing an LDD implant in the first and second channel regions through the screen oxide layer.

14. The method of claim 13 further comprising:

anisotropically etching the screen oxide layer to form spacers.

15. The method of claim 1 further comprising:

depositing an interlevel dielectric (ILD) overlying the P and N-channel TDV-TFTs;

forming a Vdd interconnect through the ILD to the first S/D region; and,

forming a Vss interconnect through the ILD to the third S/D region.

16. A method for forming a top-drain vertical thin film transistor (TDV-TFT inverter circuit, the method comprising:

forming a P-channel TDV-TFT as follows:

forming a P-channel gate connected to a gate contact, having sidewalls and a top surface, overlying a substrate insulation layer;

forming a cap oxide layer overlying the P-channel gate top surface;

forming a gate oxide layer overlying the P-channel gate sidewalls;

forming a first S/D region overlying the P-channel cap oxide layer;

forming a second S/D region overlying the substrate insulation layer, adjacent a P-channel gate first sidewall;

forming a first channel region overlying the P-channel gate first sidewall, interposed between the first and second S/D regions;

forming an N-channel TDV-TFT as follows:

forming an N-channel gate connected to the gate contact, having sidewalls and a top surface, overlying the substrate insulation layer;

forming a cap oxide layer overlying the N-channel gate top surface;

forming a third S/D region overlying the N-channel cap oxide layer;

forming a fourth S/D region overlying the substrate insulation layer, adjacent an N-channel gate first sidewall, and connected to the second S/D region; and,

forming a second channel region overlying the N-channel gate first sidewall, interposed between the third and fourth S/D regions.