IP Library Granted Patent US 7,245,166
Granted Patent B2
US 7,245,166 · App. 11/332,177 · Granted Jul 17, 2007

Starter circuit

Assignee: Aisin Seiki Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,245,166
App. No.
11/332,177
Granted
Jul 17, 2007
Kind
B2
Abstract

A starter circuit includes a start detection circuit for detecting a change of an input signal and outputting a start digital signal, a digital OR circuit for outputting a determination digital signal based on the start digital signal, a power supply circuit being activated based on the determination digital signal, and a digital control circuit being operated based on a power from the power supply circuit. The digital control circuit inputs a retention signal to the digital OR circuit for maintaining an operation of the power supply circuit and a reset signal to the start detection circuit for resetting the start detection circuit.

Claims (19)

1. A starter circuit comprising:

a start detection circuit for detecting a change of an input signal and outputting a start digital signal;

a digital OR circuit for outputting a determination digital signal based on the start digital signal;

a power supply circuit being activated based on the determination digital signal; and

a digital control circuit being operated based on a power from the power supply circuit;

wherein the digital control circuit inputs a retention signal to the digital OR circuit for maintaining an operation of the power supply circuit and a reset signal to the start detection circuit for resetting the start detection circuit.

2. A starter circuit according to claim 1 , wherein the start detection circuit is a delay flip flop circuit.

3. A starter circuit comprising:

a start detection circuit for detecting a change in an input signal and outputting a start digital signal;

a digital OR circuit for outputting a determination digital signal based on the start digital signal;

a specific circuit power supply circuit being activated based on the determination digital signal; and

a digital control circuit being operated based on a power from the specific circuit power supply circuit; and

an oscillator circuit being operated based on a power from the specific circuit power supply circuit; wherein the oscillator circuit provides a clock signal to the digital control circuit, and the digital control circuit inputs a retention signal to the digital OR circuit for maintaining an operation of the specific circuit power supply circuit and a reset signal to the start detection circuit for resetting the start detection circuit.

4. A starter circuit according to claim 3 , wherein the start detection circuit is a delay flip flop circuit.

5. A starter circuit according to claim 1 , wherein once the digital control circuit is activated, the digital control circuit brings the power supply circuit to operate by means of the retention signal in a first state outputted by the digital control circuit, and brings the power supply circuit to stop by means of the retention signal in a second state.

6. A starter circuit according to claim 1 , wherein once the digital control circuit is activated, the digital control circuit brings the power supply circuit to operate by means of the retention signal in a first state outputted by the digital control circuit, and brings the power supply circuit in a sleep state with low power consumption by means of the retention signal in a second state.

7. A starter circuit according to claim 3 , wherein the specific circuit power supply circuit starts providing a power to the oscillator circuit based on the determination digital signal.

8. A starter circuit according to claim 3 , wherein the oscillator circuit connected to the specific circuit power supply circuit generates the clock signal to be provided to the digital control circuit based on a power from the specific circuit power supply circuit.

9. A starter circuit according to claim 3 , wherein the digital control circuit performs a clock operation by means of the clock signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2006
From: KURACHI, KOHEI; INABA, HISASHI
To: AISIN SEIKI KABUSHIKI KAISHA
Reel/Frame 017786/0534 →
Priority Claims (1)
JP 2005-021341 · Jan 28, 2005 · national
Continuity (1)
Related Publication 20060170572A1 · Aug 3, 2006