IP Library Granted Patent US 7,280,313
Granted Patent B2
US 7,280,313 · App. 10/837,386 · Granted Oct 9, 2007

High aspect ratio co-planar structure fabrication consisting of different materials

Assignee: Hitachi Global Storage Technologies Netherlands B.V.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,280,313
App. No.
10/837,386
Granted
Oct 9, 2007
Kind
B2
Abstract

A a method for fabricating a structure, such as a magnetic head, having two coplanar metallic features of different compositions, both deposited on their own seed layers. The features may be made tall relative to their widths (ie. have a high aspect ratio), and are also very closely spaced. Only a single high-definition, critically aligned photolithographic procedure is used to create the critical structures, avoiding any problem with aligning features produced by multiple procedures. The method is applied to the production of the write structure of a magnetic read/write head, where a portion of the pole structure and the inductive coils are fabricated in the same plane with a close spacing and both having a vertical aspect ratio of more than about 2:1.

Claims (29)

1. A method of manufacturing a magnetic write element, comprising:

providing a substrate;

depositing a patterned multilayer seed structure, wherein said multilayer seed structure comprises:

a first electrically conductive seed layer;

a first dielectric material layer formed over said first electrically conductive seed; layer

a second electrically conductive seed; layer and

a second dielectric material layer formed over said second electrically conductive seed; layer

depositing a photoresist layer;

hard baking said photoresist layer;

patterning said hard baked photoresist layer with a mask having at least one opening;

performing a first material removal process to remove a portion of said hard baked photoresist material, wherein said material removal process is performed sufficiently to expose a portion of said first seed layer;

electroplating a first conductive material onto said exposed portion of said first seed layer;

etching openings in a portion of the exposed seed structure; and

electroplating a second electrically conductive material.

2. A method as in claim 1 , wherein said first seed layer comprises NiFe.

3. A method as in claim 1 , wherein said second seed layer comprises Cu.

4. A method as in claim 1 , wherein said first dielectric of said multilayer seed structure comprises Al 2 O 3 .

5. A method as in claim 1 , wherein said second dielectric layer of said multilayer seed structure comprises a material selected from the list consisting of SiO 2 and Si.

6. A method as in claim 1 wherein said deposited first conductive material comprises NiFe.

7. A method as in claim 1 , wherein said deposited electrically conductive material comprises Cu.

8. A method as in claim 1 , wherein said mask comprises a SiO 2 hard mask.

9. A method as in claim 1 , wherein said patterning said seed structure comprises ion milling.

10. A method as in claim 1 , wherein said patterning said seed structure comprises a liftoff process.

11. A method as in claim 1 , wherein said etching openings in a portion of the exposed seed structure comprises a reactive ion etch (RIE).

12. A method as in claim 1 , wherein said etching openings in a portion of the exposed seed layer comprises a reactive ion etch (RIE) in a fluorine containing plasma.

13. A method as in claim 1 , wherein a second material removal process comprises first performing a reactive ion etch (RIE) in an oxygen containing plasma, and thereafter performing a reactive ion etch (RIE) in a fluorine containing plasma.

14. A method as in claim 1 , further comprising, after electroplating said second electrically conductive material performing a planarization processing step.

15. A method as in claim 1 wherein said multilayer seed structure further comprises an adhesion layer formed over said second electrically conductive seed layer.

16. A method as in claim 1 , wherein said multilayer seed structure further comprises a layer of Ta formed over said second electrically conductive seed layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040819/0450 →
CHANGE OF NAME Recorded Oct 25, 2012
From: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
To: HGST NETHERLANDS B.V.
Reel/Frame 029341/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2004
From: LILLE, JEFFREY S.; NGUYEN, SON VAN; SANTINI, HUGO ALBERTO EMILIO
To: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V
Reel/Frame 015609/0550 →
Continuity (1)
Related Publication 20050243465A1 · Nov 3, 2005