Pressed-contact type semiconductor device
A P ++ -type first diffusion layer is formed by diffusing P-type impurities on a front side of an N − -type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P + -type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P + -type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
1. A pressed-contact type semiconductor device comprising:
a first conductivity type of semiconductor substrate;
a first diffusion layer formed by diffusing a second conductivity type of impurities on a first side of the semiconductor substrate;
a fourth diffusion layer formed by diffusing a first conductivity type of impurities on the first side of the semiconductor substrate so as to be shallower than the first diffusion layer;
a gate electrode provided on the first side of the semiconductor substrate so as to be in contact with the first diffusion layer;
a first electrode provided on the first side of the semiconductor substrate so as to be in contact with the fourth diffusion layer;
a second diffusion layer locally formed by diffusing the second conductivity type of impurities on a second side of the semiconductor substrate so as to be exposed on a lateral side of the substrate;
a third diffusion layer locally formed by diffusing the second conductivity type of impurities on the second side of the semiconductor substrate so as not to be exposed on the lateral side of the substrate; and
a second electrode provided on the second side of the semiconductor substrate so as to be in contact with the third diffusion layer,
wherein a lifetime control region having a lifetime shorter than that of the semiconductor substrate is formed at a periphery along the lateral side of the substrate, and an internal interface of the lifetime control region is provided inward from a portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other, and
wherein the portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other is disposed outward from the most outer diameter of the second electrode, and
a depth D 1 of the first diffusion layer from the first side of the semiconductor substrate, a depth D 2 of the second diffusion layer from the second side of the semiconductor substrate and a depth D 3 of the third diffusion layer from the second side of the semiconductor substrate have a relation of D 1 >D 2 >D 3 .
2. A pressed-contact type semiconductor device comprising:
a first conductivity type of semiconductor substrate;
a first diffusion layer formed by diffusing a second conductivity type of impurities on a first side of the semiconductor substrate;
a fourth diffusion layer formed by diffusing a first conductivity type of impurities on the first side of the semiconductor substrate so as to be shallower than the first diffusion layer;
a gate electrode provided on the first side of the semiconductor substrate so as to be in contact with the first diffusion layer;
a first electrode provided on the first side of the semiconductor substrate so as to be in contact with the fourth diffusion layer;
a second diffusion layer locally formed by diffusing the second conductivity type of impurities on a second side of the semiconductor substrate so as to be exposed on a lateral side of the substrate;
a third diffusion layer locally formed by diffusing the second conductivity type of impurities on the second side of the semiconductor substrate so as not to be exposed on the lateral side of the substrate; and
a second electrode provided on the second side of the semiconductor substrate so as to be in contact with the third diffusion layer,
wherein a lifetime control region having a lifetime shorter than that of the semiconductor substrate is formed at a periphery along the lateral side of the substrate, and an internal interface of the lifetime control region is provided inward from a portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other, and
wherein the portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other is disposed outward from the most outer diameter of the second electrode,
a bevel surface having a concave cross-section is formed along a lateral side of the semiconductor substrate, and
a diameter Eb where an internal interface of the second diffusing layer and an internal interface of the third diffusion layer intersect with each other is less than an innermost diameter Fb of the bevel surface.
3. The pressed-contact type semiconductor device according to claim 2 , wherein the diameter Eb is greater than an outermost diameter Ea of the second electrode.
4. The pressed-contact type semiconductor device according to claim 2 , wherein the innermost diameter Fb of the bevel surface, the diameter Eb, the outermost diameter Ea of the second electrode, and an innermost diameter Fa of an internal interface of the lifetime control region have a relation of Fb>Eb>Ea>Fa.
5. A pressed-contact type semiconductor device comprising:
a first conductivity type of semiconductor substrate;
a first diffusion layer formed by diffusing a second conductivity type of impurities on a first side of the semiconductor substrate;
a fourth diffusion layer formed by diffusing a first conductivity type of impurities on the first side of the semiconductor substrate so as to be shallower than the first diffusion layer;
a gate electrode provided on the first side of the semiconductor substrate so as to be in contact with the first diffusion layer;
a first electrode provided on the first side of the semiconductor substrate so as to be in contact with the fourth diffusion layer;
a second diffusion layer locally formed by diffusing the second conductivity type of impurities on a second side of the semiconductor substrate so as to be exposed on a lateral side of the substrate;
a third diffusion layer locally formed by diffusing the second conductivity type of impurities on the second side of the semiconductor substrate so as not to be exposed on the lateral side of the substrate; and
a second electrode provided on the second side of the semiconductor substrate so as to be in contact with the third diffusion layer,
wherein a lifetime control region having a lifetime shorter than that of the semiconductor substrate is formed at a periphery along the lateral side of the substrate, and an internal interface of the lifetime control region is provided inward from a portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other, and
wherein the portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other is disposed outward from the most outer diameter of the second electrode,
a bevel surface having a concave cross-section is formed along a lateral side of the semiconductor substrate, and
a diameter Eb where an internal interface of the second diffusing layer and an internal interface of the third diffusion layer intersect with each other, an outermost diameter Ea of the second electrode, and a depth D 2 of the second diffusion layer have a relation of Eb−Ea>2×D 2 .
6. A pressed-contact type semiconductor device comprising:
a first conductivity type of semiconductor substrate;
a first diffusion layer formed by diffusing a second conductivity type of impurities on a first side of the semiconductor substrate;
a fourth diffusion layer formed by diffusing a first conductivity type of impurities on the first side of the semiconductor substrate so as to be shallower than the first diffusion layer;
a gate electrode provided on the first side of the semiconductor substrate so as to be in contact with the first diffusion layer;
a first electrode provided on the first side of the semiconductor substrate so as to be in contact with the fourth diffusion layer;
a second diffusion layer locally formed by diffusing the second conductivity type of impurities on a second side of the semiconductor substrate so as to be exposed on a lateral side of the substrate;
a third diffusion layer locally formed by diffusing the second conductivity type of impurities on the second side of the semiconductor substrate so as not to be exposed on the lateral side of the substrate; and
a second electrode provided on the second side of the semiconductor substrate so as to be in contact with the third diffusion layer,
wherein a lifetime control region having a lifetime shorter than that of the semiconductor substrate is formed at a periphery along the lateral side of the substrate, and an internal interface of the lifetime control region is provided inward from a portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other, and
wherein the portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other is disposed outward from the most outer diameter of the second electrode,
a bevel surface having a concave cross-section is formed along a lateral side of the semiconductor substrate, and
the diameter Eb where an internal interface of the second diffusing layer and an internal interface of the third diffusion layer intersect with each other, a most outer diameter Ec of the fourth diffusion layer, and a distance D 5 between an internal interface of the first diffusion layer and an internal interface of the third diffusion layer have a relation of Ec<Eb−D 5 .