System and method for assembling a data packet
Disclosed is a system and method for assembling a data packet. The system can be implemented as four memory elements associated with one or more processors. The first memory element stores a sequence number and a sub-channel identifier for an incoming data packet. The second memory element stores a revised packet fragment. The third memory element stores an unrevised packet fragment. The fourth memory element stores a starting address. In the system, the starting address may be the starting address of the revised packet fragment or the unrevised packet fragment wherein the first memory element identifies portions of the fourth memory element associated with the sequence number. The one or more processors are configured to create a modified data packet by combining the unrevised packet fragments and the revised packet fragment, wherein the modified data packet is associated with the sequence number and sub-channel identifier.
1. A system for assembling a data packet, the system comprising:
a first memory element for storing a sequence number and a sub-channel identifier for an incoming data packet;
a second memory element for storing one or more revised packet fragment;
a third memory element for storing one or more unrevised packet fragment;
a fourth memory element for storing a starting address, wherein the starting address may be the starting address of a revised packet fragment or the starting address of an unrevised packet fragment, wherein the first memory element identifies portions of the fourth memory element associated with the sequence number; and
one or more processors, wherein the one or more processors are configured to create a modified data packet by combining the one or more unrevised packet fragments and the one or more revised packet fragments, wherein the modified data packet is associated with the sequence number and the sub-channel identifier.
2. The system for assembling a data packet of claim 1 , wherein the one or more processors create the modified data packet from 64-bit bursts.
3. The system for assembling a data packet of claim 1 , wherein the one or more unrevised packet fragments are 64-bit words unaligned.
4. The system for assembling a data packet of claim 1 , wherein the one or more revised packet fragments are 64-bit words aligned.
5. The system for assembling a data packet of claim 1 , wherein the incoming data packet is a datagram.
6. The system for assembling a data packet of claim 1 , wherein entries in the fourth memory element are organized as a bit validity field, a size of data field, and a location of data field.
7. A method for assembling a data packet, the method comprising steps of:
storing a sequence number and a sub-channel identifier for an incoming data packet in a first memory element;
storing one or more revised packet fragment;
storing one or more unrevised packet fragment;
storing a starting address in a second memory element, wherein the starting address may be the starting address of a revised packet fragment or the starting address of an unrevised packet fragment, wherein the first memory element identifies portions of the second memory element associated with the sequence number; and
creating a modified data packet by combining the one or more unrevised packet fragments and the one or more revised packet fragments, wherein the modified data packet is associated with the sequence number and the sub-channel identifier.
8. The method for assembling a data packet of claim 7 , wherein the step of creating a modified data packet includes creating the modified data packet from 64-bit bursts.
9. The method for assembling a data packet of claim 7 , wherein the one or more unrevised packet fragments are 64-bit words unaligned.
10. The method for assembling a data packet of claim 7 , wherein the one or more revised packet fragments are 64-bit words aligned.
11. The method for assembling a data packet of claim 7 , wherein the incoming data packet is a datagram.
12. The method for assembling a data packet of claim 7 , wherein entries in the second memory element are organized as a bit validity field, a size of data field, and a location of data field.
13. A system for assembling a data packet, the system comprising:
means for storing a sequence number and a sub-channel identifier for an incoming data packet in a first memory element;
means for storing one or more revised packet fragment;
means for storing one or more unrevised packet fragment;
means for storing a starting address in a second memory element, wherein the starting address may be the starting address of a revised packet fragment or the starting address of an unrevised packet fragment, wherein the first memory element identifies portions of the second memory element associated with the sequence number; and
means for creating a modified data packet by combining the one or more unrevised packet fragments and the one or more revised packet fragments, wherein the modified data packet is associated with the sequence number and the sub-channel identifier.
14. The system for assembling a data packet of claim 13 , wherein the means for creating a modified data packet includes means for creating the modified data packet from 64-bit bursts.
15. The system for assembling a data packet of claim 13 , wherein the one or more unrevised packet fragments are 64-bit words unaligned.
16. The system for assembling a data packet of claim 13 , wherein the one or more revised packet fragments are 64-bit words aligned.
17. The system for assembling a data packet of claim 13 , wherein the incoming data packet is a datagram.
18. The system for assembling a data packet of claim 13 , wherein entries in the second memory element are organized as a bit validity field, a size of data field, and a location of data field.