IP Library Granted Patent US 7,307,322
Granted Patent B2
US 7,307,322 · App. 11/252,493 · Granted Dec 11, 2007

Ultra-uniform silicide system in integrated circuit technology

Assignee: Adavnced Micro Devices, Inc.
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Quick Facts
Patent No.
US 7,307,322
App. No.
11/252,493
Granted
Dec 11, 2007
Kind
B2
Abstract

A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

Claims (26)

1. An integrated circuit comprising:

a semiconductor substrate having source/drain junctions;

a gate dielectric on the semiconductor substrate;

a gate over the gate dielectric;

ultra-uniform silicides on the source/drain junctions;

a dielectric layer above the semiconductor substrate; and

contacts in the dielectric layer to the ultra-uniform silicides.

2. The integrated circuit as claimed in claim 1 wherein:

the ultra-uniform silicides is an ultra-thin thickness of a silicide metal of not more than 50 Å thick.

3. The integrated circuit as claimed in claim 1 wherein:

the dielectric layer deposits a dielectric material having a dielectric constant selected from a group consisting of medium, low, and ultra-low dielectric constants.

4. The integrated circuit as claimed in claim 1 wherein:

the contacts to the ultra-uniform silicides are of materials selected from a group consisting of tantalum, titanium, tungsten, copper, gold, silver, an alloy thereof, a compound thereof, and a combination thereof.

5. An integrated circuit comprising:

a silicon substrate having source/drain junctions;

a gate oxide on the silicon substrate;

a polysilicon gate over the gate oxide;

an ultra-uniform nickel silicide on the source/drain junctions and the polysilicon gate, the ultra-uniform nickel silicide having no variations in thickness greater than 3% of the overall thickness;

a dielectric layer above the silicon substrate; and

contacts in the dielectric layer to the ultra-uniform nickel silicide.

6. The integrated circuit as claimed in claim 5 wherein:

the ultra-uniform nickel silicide is an ultra-thin thickness of a silicide metal of not more than 50 Å thickness.

7. The integrated circuit as claimed in claim 5 wherein:

the dielectric layer is a dielectric material having a dielectric constant below 4.2.

8. The integrated circuit as claimed in claim 5 wherein:

the contacts to the ultra-uniform silicides are of materials selected from a group consisting of tantalum, titanium, tungsten copper, gold, silver, an alloy thereof, a compound thereof, and a combination thereof.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2021
From: FULLBRITE CAPITAL PARTNERS
To: OCEAN SEMICONDUCTOR LLC
Reel/Frame 058497/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2021
From: ADVANCED MICRO DEVICES, INC.
To: FULLBRITE CAPITAL PARTNERS
Reel/Frame 055766/0694 →
SECURITY INTEREST Recorded Apr 10, 2019
From: ADVANCED MICRO DEVICES, INC.
To: FULLBRITE CAPITAL PARTNERS, LLC
Reel/Frame 048844/0693 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2019
From: CHIU, ROBERT J.; PATTON, JEFFREY P.; BESSER, PAUL R.; NGO, MINH VAN
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 048697/0419 →
Continuity (2)
Division 1061508600 · Jul 7, 2003
Related Publication 20060267107A1 · Nov 30, 2006