Interconnection structure of integrated circuit chip
An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.
1. An interconnection structure comprising:
an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit;
a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal;
an input/output (I/O) pad, the I/O pad including a first portion in contact with the terminal and a second portion that extends over the passivation layer; and
an electroless plating layer disposed on the I/O pad, the electroless plating layer comprising nickel and plating core particles formed over an opening and over a portion of the passivation layer.
2. The structure of claim 1 , the I/O pad comprising at least one selected from the group consisting of aluminum and copper.
3. The structure of claim 1 , further comprising a polymer layer disposed on the passivation layer.
4. The structure of claim 3 , the polymer layer disposed under the second portion of the I/O pad.
5. The structure of claim 3 , the polymer layer disposed on a peripheral edge of the second portion of the I/O pad.
6. The structure of claim 1 , further comprising a metal bump disposed on the electroless plating layer.
7. The structure of claim 6 , the metal bump substantially aligned with the terminal in a vertical direction.
8. The structure of claim 6 , the metal bump not aligned with the terminal in a vertical direction.
9. The structure of claim 1 , the electroless plating layer further comprising phosphorus or boron.
10. The structure of claim 1 , further comprising a gold layer coating the electroless plating layer.
11. The structure of claim 1 , the electroless plating layer comprising zinc particles.
12. The structure of claim 1 , the terminal comprising tungsten.
13. An interconnection structure comprising:
an integrated circuit (IC) chip having a terminal that is electrically connected to an internal circuit of the IC chip, the terminal including tungsten;
a passivation layer disposed on a top surface of the IC chip, the passivation layer having an opening that exposes the terminal;
a polymer layer disposed on a top surface of the passivation layer, the polymer layer having an opening that exposes the terminal and a portion of the passivation layer;
an input/output (I/O) pad including aluminum, the I/O pad disposed over the polymer layer such that the I/O pad directly contacts the exposed portion of the terminal, directly contacts the exposed portion of the passivation layer, and directly contacts a portion of polymer layer; and
an electroless plating layer disposed on the I/O pad, the electroless plating layer including nickel and including zinc particles formed over the opening and over a portion of the polymer layer.
14. The structure of claim 13 , further comprising a metal bump disposed on the electroless plating layer.
15. The structure of claim 14 , the metal bump disposed to overlap the terminal.
16. The structure of claim 14 , the metal bump disposed to not overlap the terminal.
17. An interconnection structure comprising:
an integrated circuit (IC) chip having a terminal that is electrically connected to an internal circuit of the IC chip;
a passivation layer disposed on a top surface of the IC chip, the passivation layer having an opening that exposes the terminal;
an input/output (I/O) pad, the I/O pad disposed in the opening and on the passivation layer; and
an electroless plating layer disposed on the I/O pad, the electroless plating layer including plating core particles formed over the opening and over a portion of the passivation layer.
18. The structure of claim 17 , wherein the I/O pad includes a first portion disposed in the opening to be in contact with the terminal and a second portion that extends over the passivation layer, wherein a section of the second portion of the I/O pad is configured as a test pad that is separated from the terminal and used during an electrical die sorting test to prevent damage to the first portion of the I/O pad.
19. The structure of claim 17 , wherein the I/O pad is formed of a first material and the electroless plating layer is formed of a second material, the first material being different from the second material.