IP Library Granted Patent US 7,317,622
Granted Patent B2
US 7,317,622 · App. 10/334,807 · Granted Jan 8, 2008

Method and apparatus for supplying power to a semiconductor device using a capacitor DC shunt

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,317,622
App. No.
10/334,807
Granted
Jan 8, 2008
Kind
B2
Abstract

A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.

Claims (7)

1. A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard, said device further of a type having a spaced portion located between the motherboard and the package, the power shunt comprising:

a capacitor adapted to be positioned within the spaced portion between the motherboard and the package of the semiconductor device, said capacitor having a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer,

wherein said first type conductive layer and second type conductive layer are adapted to form a conductive bridge along an outside of the capacitor between the motherboard and the package.

2. The power shunt of claim 1 , wherein said first type conductive layer is coupled to a different voltage source from the second type conductive layer in order to provide a capacitance between the two layers types.

3. The power shunt of claim 1 , further including terminals of a first type and a second type located along a first side of the capacitor and along an opposing side of the capacitor, said terminals coupled to respective type conductive layers of the capacitor.

4. The power shunt of claim 2 , wherein said first type conductive layer is coupled to power source and said second conductive layer is coupled to a ground source.

5. The power shunt of claim 2 , said capacitor including a plurality of conductive layers of a first type and a plurality of conductive layers of a second type electrically isolated from the layers of the first type by a plurality of dielectric layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2003
From: LI, YUAN-LIANG
To: INTEL CORPORATION
Reel/Frame 013967/0050 →
Continuity (1)
Related Publication 20040124511A1 · Jul 1, 2004