Method and apparatus for data bit align

1. An apparatus for data bit align, comprising:

a pipeline sample word aligner for a time frame alignment of a clock sample word with a time frame alignment of a data sample word;

a multiplexer that receives the data sample word, the data sample word including a plurality of data bits, as data input and that receives the clock sample word from the pipeline sample word aligner, the clock sample word including a plurality of clock bits wherein a bit state of one of the plurality of clock bits represents a clock edge, as select input,

wherein the multiplexer selects a data bit from the plurality of data bits in the data sample word based on a position of the clock edge in the clock sample word, the data sample word and the clock sample word are of same size and if the clock sample word includes the clock edge, the selected data bit is a bit in the data sample word corresponding to a bit representing the clock edge in the clock sample word, and if the clock sample word does not include the clock edge, the selected data bit is NULL.

2. An apparatus as recited in claim 1 , wherein the clock sample word indicates the position of the clock edge.

3. An apparatus as recited in claim 2 , wherein the position of a clock edge is indicated by a bit state in the clock sample word.

4. An apparatus as recited in claim 3 , wherein the position of a clock edge is indicated by a TRUE bit value.

5. An apparatus as recited in claim 4 , wherein a TRUE bit value is indicated by a bit having a value of “1.”

6. An apparatus as recited in claim 1 , wherein the multiplexer selects a data bit from the data sample word based on a position of a clock edge in the clock sample word.

7. An apparatus as recited in claim 6 , wherein the multiplexer selects the data bit from the data sample word corresponding to the position of the clock edge in the clock sample word.

8. An apparatus as recited in claim 7 , wherein the clock edge is indicated by a bit having a value of “1” and remaining bits of the clock sample word have a value of “0.”

9. An apparatus as recited in claim 1 , further comprising an output register coupled to the multiplexer, the output register storing the selected data bit from the multiplexer and providing the selected data bit to remaining system components.

10. An apparatus as recited in claim 9 , wherein remaining system components ignore data bits stored in the output register when the clock sample word comprises only bits having a value of “0.”

11. A method for providing data bit align, comprising the operations of:

receiving a data sample word comprising a plurality of data bits;

receiving a clock sample word comprising a plurality of clock bits wherein a bit state of one of the plurality of clock bits represents a clock edge;

determining a position of the clock edge within the clock sample word when the clock edge is present in the clock sample word; and

selecting a data bit from the data sample word based on the position of the clock edge within the clock sample word when the clock edge is present in the clock sample word,

wherein the data sample word and the clock sample word are of same size and if the clock sample word includes the clock edge, the selected data bit is a bit in the data sample word corresponding to a bit representing the clock edge in the clock sample word, and if the clock sample word does not include the clock edge, the selected data bit is NULL.

12. A method as recited in claim 11 , wherein the bit state having a value of TRUE indicates the clock edge.

13. A method as recited in claim 12 , wherein the clock sample word comprises all bits having a value of FALSE when a clock edge is not present in the clock sample word.

14. A method as recited in claim 13 , further comprising the operation of selecting the data bit from the data sample word in the same bit position as the bit having a value of TRUE in the sample clock word when the clock edge is present in the clock sample word.

15. A method as recited in claim 11 , further comprising the operation of providing the selected data bit to remaining system components when the clock edge is present in the clock sample word.

16. A method as recited in claim 15 , wherein the remaining system components ignore the selected data bit when the clock edge is not present in the clock sample word.

17. A system for data bit align, comprising:

a multiplexer that receives a data sample word, the data sample word including a plurality of data bits, as data input and that receives a clock sample word the clock sample word including a plurality of clock bits wherein a bit state of one of the plurality of clock bits represents a clock edge, as select input, wherein the multiplexer selects a data bit from the plurality of data bits in the data sample word based on a position of the clock edge in the clock sample word; and

an output register directly coupled to the multiplexer, the output register storing the selected data bit from the multiplexer during an internal clock cycle and providing the selected data bit to remaining system components during the next internal clock cycle,

wherein the data sample word and the clock sample word are of same size and if the clock sample word includes the clock edge, the selected data bit is a bit in the data sample word corresponding to a bit representing the clock edge in the clock sample word, and if the clock sample word does not include the clock edge, the selected data bit is NULL.

18. A system as recited in claim 17 , wherein the multiplexer selects the data bit from the data sample word corresponding to a position of the clock edge in the clock sample word.

19. A system as recited in claim 18 , wherein the clock edge is indicated by a bit having a value of “1” and remaining bits of the clock sample word have a value of “0.”

20. A system as recited in claim 19 , wherein remaining system components ignore data bits stored in the output register when the clock sample word comprises only bits having a value of “0.”