Method of fabricating gate electrode of semiconductor device
View Patent ↗A method of forming a gate electrode of a semiconductor device includes forming a damascene pattern for fabricating a metal electrode on an upper part of a poly silicon gate so as to prevent a metal electrode from being oxidized when the poly silicon electrode and the metal electrode are formed simultaneously. The method of forming the gate electrode of the semiconductor device includes the steps of forming a gate including poly silicon with a plurality of layers at an upper part of a silicon substrate, forming a spacer on a sidewall of the gate, vapor depositing inter layer dielectric between gates at the upper part of the substrate, forming a damascene pattern to which a metal electrode is formed, and completing the gate electrode including poly silicon and metal by filling the damascene pattern with a predetermined metal and planarizing the metal.
1. A method for forming a gate electrode of a semiconductor device, comprising the steps of:
forming a gate with a material that includes poly silicon with a plurality of layers at an upper part of a silicon substrate;
forming a spacer on a sidewall of the gate by etching a nitride film so that the spacer has a height less than that of the gate;
vapor depositing an inter layer dielectric between the gate and an adjacent gate at the upper part of the substrate;
forming a damascene pattern so as to form a metal electrode; and
completing the gate electrode including poly silicon and metal by filling the damascene pattern with a predetermined metal and planarizing the metal.
2. The method of claim 1 , wherein the step of forming the gate comprises the steps of:
forming a device separating film at an upper part of the silicon substrate;
sequentially stacking a gate oxide film, a first poly silicon, a buffer oxide film, and a second poly silicon material on an upper surface of the substrate; and
completing the step of forming the gate by etching at least one layer of the plurality of layers using the pattern as an etch mask.
3. The method of claim 2 , wherein, for the etching step, dry etch is employed using plasma.
4. The method of claim 2 , wherein the second poly silicon has a thickness in an inclusive range of 60 .ANG. to 1500 .ANG.
5. The method of claim 2 , wherein the buffer oxide film has a thickness in an inclusive range of 120 .ANG. to 300 .ANG.
6. The method of claim 2 , wherein the second poly silicon serves a function of setting a height of the metal electrode, and controlling a thickness of vapor deposition according to a predetermined device characteristic.
7. The method of claim 1 , wherein the step of forming the spacer on the gate sidewall comprises the steps of: vapor depositing the second buffer oxide film and a nitride film on the substrate having the poly silicon gate with a thickness of T 1 .
8. The method of claim 7 , wherein, for etching the nitride film, dry etching is employed using plasma.
9. The method of claim 7 , wherein the second buffer oxide film is in an inclusive range of 150 .ANG. to 400 .ANG. thick.
10. The method of claim 7 , wherein the nitride film is in an inclusive range of 700 .ANG. to 1500 .ANG. thick.
11. The method of claim 7 , wherein the thickness of the nitride film is changed according to a performance characteristic of a device, and to a predetermined circuit structure.
12. The method of claim 1 , wherein a thickness of the inter layer dielectric between gates is thicker than that of the poly silicon gate.
13. The method of claim 1 , wherein the step of vapor depositing an inter layer dielectric includes planarizing the inter layer dielectric by at least one of CMP and a dry etch-back method.
14. The method of claim 2 , wherein step of sequentially stacking includes planarizing by CMP using the second poly silicon as a stop.
15. The method of claim 2 , further comprising planarizing the inter layer dielectric with a CMP process by time polishing to a predetermined height higher than the second poly silicon, and further comprising at least one of wet etching and plasma dry etching the plurality of layers.
16. The method of claim 2 , wherein the step of forming the damascene pattern comprises a step of removing the second poly silicon and the buffer oxide film.
17. The method of claim 16 , wherein the step of removing the second poly silicon and the buffer oxide film is carried out by the dry etch using chemical.
18. The method of claim 1 , wherein the step of planarizing the metal of the damascene pattern is carried out by at least one of CMP and dry etch-back.