IP Library Granted Patent US 7,352,067
Granted Patent B2
US 7,352,067 · App. 11/166,229 · Granted Apr 1, 2008

Stacked semiconductor device

Assignees: NEC Corporation; Elpida Memory, Inc.
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Quick Facts
Patent No.
US 7,352,067
App. No.
11/166,229
Granted
Apr 1, 2008
Kind
B2
Abstract

A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Claims (19)

1. A stacked semiconductor device comprising:

a plurality of semiconductor chips, said semiconductor chips being stacked together; and

a conductive path from a first terminal to a second terminal extending through at least one of said semiconductor chips;

wherein said semiconductor chips are electrically connected by said conductive path, and each conductive path has a plurality of through-connections extending through the at least one semiconductor chip; and

wherein each of the plurality of through-connections is routed through a through-via, said through-via comprising a hole in the at least one semiconductor chip.

2. The device according to claim 1 , wherein said through-connections have electrically identical characteristics.

3. The device according to claim 1 , wherein said through-connections are connected parallel to each other.

4. The device according to claim 1 , further comprising a switch circuit connected to said through-connections for selectively using a normal one of said through-connections as a signal path.

5. The device according to claim 4 , wherein said switch circuit separates a faulty one of said through-connections.

6. The device according to claim 4 , wherein said switch circuit is associated with each of said semiconductor chips.

7. The device according to claim 4 , wherein said switch circuit comprises a tristate circuit.

8. The device according to claim 7 , wherein said switch circuit comprises a transfer gate.

9. The stacked semiconductor device according to claim 4 , wherein said through-connections include primary faulty through-connections and backup through-connections, each of said primary faulty through-connections being associated with a plurality of said backup through-connections, and wherein said switch circuit switches each of said primary faulty through-connections to either one of said backup through-connections.

10. The stacked semiconductor device according to claim 9 , wherein the number of said primary faulty through-connections and the number of said backup through-connections are equal to each other.

11. The stacked semiconductor device according to claim 1 , wherein said through-connections include primary faulty through-connections and backup through-connections, each of said backup through-connections being shared by a plurality of said primary faulty through-connections.

12. The stacked semiconductor device according to claim 4 , wherein said switch circuit has a function to detect a failure or a performance deterioration of said through-connections.

13. The stacked semiconductor device according to claim 12 , wherein said switch circuit separates one of the through-connections whose failure or performance deterioration is detected, and switches to another one of the through-connections.

14. The stacked semiconductor device according to claim 1 , wherein said through-connections include primary faulty through-connections and backup through-connections, each of said semiconductor chips having a plurality of functional circuits, said primary faulty through-connections being connected to said functional circuits, each of said backup through-connections being associated with and shared by at least two of said primary connections.

15. The stacked semiconductor device according to claim 14 , wherein each of said backup through-connections is disposed between said functional circuits to which said primary connections sharing said backup through-connection are connected.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2005
From: FUKAISHI, MUNEO; SAITO, HIDEAKI; HAGIHARA, YASUHIKO; MIZUNO, MASAYUKI; IKEDA, HIROAKI; SHIBATA, KAYOKO
To: NEC CORPORATION; ELPIDA MEMORY INC.
Reel/Frame 016732/0947 →
Priority Claims (1)
JP 2004-192763 · Jun 30, 2004 · national
Continuity (1)
Related Publication 20060001176A1 · Jan 5, 2006