IP Library Granted Patent US 7,397,456
Granted Patent B2
US 7,397,456 · App. 10/831,103 · Granted Jul 8, 2008

Inspecting method and inspecting device of control signal for display device, and display unit having this inspecting function

Assignee: Hitachi Displays, Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,397,456
App. No.
10/831,103
Granted
Jul 8, 2008
Kind
B2
Abstract

The states of various kinds of control signals, such as a horizontal synchronizing signal, a vertical synchronizing signal, a display timing signal, etc., that are supplied from an external signal source to a display device, are inspected. In the states of various kinds of control signals supplied from the external signal source HOST to the display device DSP, (1) the vertical synchronizing signal (VSYNC) is converted into a display signal of red (R), (2) the horizontal synchronizing signal (HSYNC) is converted into a display signal of green (G), and (3) the display timing signal is converted into a display signal of blue (B) by a control signal inspecting circuit. The states are displayed in color and brightness on the screen of the display device DSP, so that these states can be simply visually inspected.

Claims (33)

1. A control signal inspecting device for a display device for displaying an indication of the existence of an abnormality of plural control signals inputted from an external signal source on the screen of the display device, comprising:

a display device for inspection at a resolution equal to or higher than that of said display device; and

a display controller having a timing controller having a control signal inspecting circuit for generating control signals including a horizontal synchronizing signal, a vertical synchronizing signal and a display timing signal on the basis of various kinds of synchronizing signals inputted from said external signal source,

wherein said control signal inspecting circuit has:

a plural-pixel counter for setting a clock corresponding to plural pixels determined in advance to a parameter clock, and counting the pixels corresponding to the number of parameter clocks;

a decoder for converting each of the horizontal synchronizing signal, the vertical synchronizing signal and the display timing signal as said control signals into red (R) data, green (G) data and blue (B) data;

a delay circuit for delaying each of said control signals by a constant time;

a shift register having the capacity of said parameter clocks for storing each of said control signals delayed by said delay circuit;

a line memory having the capacity of about the resolution of said display device for inspection in the horizontal direction, and respectively converting output data of said shift register into red (R) data, green (G) data and blue (B) data by said decoder and storing the converted data;

an address counter for designating the address of an input port when each output data of said decoder are stored to said line memory;

an end register for storing a final address of said address counter;

a start counter for designating an output address of said line memory in accordance with the stored data of said end register; and

a data control circuit arranged on the output side of said line memory and comparing the stored data of said address counter and said end register, and selecting the red (R) data, the green (G) data and the blue (B) data outputted to said display device and its brightness by the comparison result.

2. The control signal inspecting device according to claim 1 , wherein

said control signal inspecting circuit further has an interval check circuit for detecting the number of clocks from a horizontal synchronizing signal to the next horizontal synchronizing signal, and performing generation and non-generation of a line reset signal.

3. A display unit comprising:

a display controller having a timing controller having a control signal inspecting circuit for generating control signals including a horizontal synchronizing signal, a vertical synchronizing signal and a display timing signal;

a decoder for converting each of said horizontal synchronizing signal, said vertical synchronizing signal and said display timing signal into one of red (R) data, green (G) data and blue (B) data;

a display device for displaying the converted data;

a delay circuit for delaying the output of said control signal;

a line memory for storing the data converted by said decoder;

wherein said display controller has a plural-pixel counter for setting a clock corresponding to plural pixels determined in advance to a parameter clock, and counting the pixels corresponding to the parameter clock number;

a shift register having a capacity of said parameter clocks;

an address counter for designating the address of an input port when each output data of said decoder are stored to said line memory;

an end register for storing a final address of said address counter;

a start counter for designating an output address of said line memory in accordance with the stored data of said end register; and

a data control circuit arranged on the output side of said line memory and comparing the stored data of said address counter and said end register and selecting the red (R) data, the green (G) data and the blue (B) data and its brightness outputted to said display device by the comparison result.

4. The display unit according to claim 3 , wherein

output data switching means for switching normal display data and display data from said control signal inspecting circuit is arranged in said timing controller.

5. The display unit according to claim 3 , wherein

said display controller generates the control signal including the horizontal synchronizing signal, the vertical synchronizing signal and the display timing signal on the basis of various kinds of synchronizing signals inputted from the exterior.

6. The display unit according to claim 3 , wherein

the states of said horizontal synchronizing signal, said vertical synchronizing signal and said display timing signal are displayed by changing the brightnesses of the red (R) data, the green (G) data and the blue (B) data.

Assignments (3)
COMPANY SPLIT PLAN TRANSFERRING FIFTY (50) PERCENT SHARE OF PATENTS Recorded Oct 14, 2011
From: HITACHI DISPLAYS, LTD.
To: IPS ALPHA SUPPORT CO., LTD.
Reel/Frame 027063/0019 →
MERGER Recorded Oct 14, 2011
From: IPS ALPHA SUPPORT CO., LTD.
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027063/0139 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2004
From: IGARASHI, YOICHI
To: HITACHI DIPLAYS, LTD.
Reel/Frame 015265/0887 →
Priority Claims (1)
JP 2003-119771 · Apr 24, 2003 · national
Continuity (1)
Related Publication 20040212609A1 · Oct 28, 2004