Implementation technique for linear phase equalization in multi-mode RF transmitters
The present invention implements an architecture that changes the sequence of digital processing so that equalization occurs prior to phase accumulation. A phase differentiator receives an envelope path phase signal to produce a differentiated phase signal to an equalizer. The transfer function of the phase differentiator is implemented so that it cancels, except for a one-cycle delay, the transfer function of the phase accumulator. This cancellation substantially eliminates accumulation of the envelop path phase signal. Additionally, a dither signal added to the quantization nodes in the equalizers shifts the spectral content of the quantization noise such that the phase accumulator sees the quantization noise as zero mean white noise. Implemented as one of a rounding or flooring quantizer, biquad filters in the equalizers round or truncate the equalizer output to a minimal bit width based on a desired output phase error.
1. A multi-mode RF polar transmitter, comprises:
digital modulator operable to produce phase-shift keying (PSK) filtered symbols and filtered Gaussian Minimum Shift Keying (GMSK) phase signals;
envelope path adjustment circuitry coupled to received the PSK filtered symbols and operable to produce an envelope signal; and
phase path adjustment circuitry, comprising:
phase differentiator coupled to receive a phase signal from the envelope path adjustment circuitry and operable to differentiate phase information produced in the phase path adjustment circuitry for a PSK modulation to produce differentiated phase signals to the envelope path adjustment circuitry wherein, for a GMSK modulation, when phase accumulated in the phase path adjustment circuitry, neutralizes phase accumulation of the phase signal received from the envelope path adjustment circuitry;
summing node operably coupled to sum the differentiated PSK phase signals and GMSK phase signals to produce summed phase signals;
phase magnitude and group delay equalizer operably coupled to receive the summed phase signals to produce phase output signals with a phase error less than or equal to a specified value;
phase accumulator for accumulating the phase output signals to produce accumulated phase output signal;
direct digital frequency synthesizer (DDFS) coupled to receive the accumulated phase output signal to produce I and Q components of the accumulated phase output signal; and
phase signal interpolator for producing an up-converted RF phase accumulated signal based upon the I and Q component accumulated phase output signal.
2. The multi-mode RF polar transmitter of claim 1 wherein the phase magnitude and group delay equalizer includes a plurality of second order infinite impulse response (IIR) filters.
3. The multi-mode RF polar transmitter of claim 2 wherein the IIR filters includes:
a plurality of coarse quantization nodes and fine quantization nodes; and
at least one uncorrelated dither signal that reduces IIR filter phase error.
4. The multi-mode RF polar transmitter of claim 3 wherein the plurality of coarse and fine quantization nodes are implemented as one of a rounding quantizer or a flooring quantizer that rounds or truncates an N-bit multiplicand to an L-bit result wherein L is less than N.
5. The multi-mode RF polar transmitter of claim 4 wherein the L-bit and N-bit result are derived as a minimal solution for a desired maximum phase accumulator output phase error.
6. A method for linear phase equalization in an RF polar transmitter, the method comprising:
receiving a first phase signal from an envelope path adjustment circuitry;
differentiating the first phase signal to produce a differentiated phase signal;
receiving a second phase signal conducted within phase path adjustment circuitry;
summing the differentiated phase signal and the second phase signal to produce a summed phase signal;
equalizing a magnitude and group delay of the summed phase signal; and
accumulating the summed phase signal in a phase accumulator to produce a linear phase signal.
7. The method of claim 6 wherein the differentiated phase signal is produced by a phase differentiator that introduces a transfer function that substantially cancels a transfer function introduced by the phase accumulator.
8. The method of claim 6 wherein the step of equalizing the magnitude and group delay comprises:
operably coupling the summed phase signal to a plurality of biquads wherein a first plurality of biquads performs a low pass filter function;
operably coupling the low pass filtered summed phase signal to a second plurality of biquads that performs an all pass filter function; and
quantizing an output of the plurality of biquads to a minimal bit width based on a desired maximum phase error.
9. The method of claim 8 wherein the plurality of biquads are implemented as a second order IIR filter.
10. The method of claim 8 wherein quantizing the output of the plurality of biquads includes injecting one of a flooring equalizer and a rounding equalizer to each quantization node.
11. The method of claim 8 wherein quantizing the output of the plurality of biquads further includes adding a dither signal to each biquad quantization node to spectrally shift quantization noise to white noise.