Precision capacitor array
A digital capacitor array with individually shielded unit capacitors and combination binary—thermometer coded addressing is disclosed. Such a capacitor array may be part of a digitally controlled oscillator in a MEMS-based frequency reference.
1. A capacitor array comprising:
a plurality of unit capacitors addressed with a monotonic combination binary-thermometer coded addressing scheme and comprising binary coded capacitor groups and thermometer coded capacitor groups, wherein:
the unit capacitors are arranged in a common-centroid layout;
the binary coded capacitor groups are located closer to the center of the common-centroid layout than the thermometer coded capacitor groups; and
each unit capacitor is electrically shielded from one or more neighbor capacitors.
2. The capacitor array of claim 1 further comprising dummy capacitor groups located farther from the center of the common-centroid layout than are the thermometer coded capacitor groups.
3. The capacitor array of claim 1 wherein each unit capacitor is electrically shielded from array address lines.
4. The capacitor array of claim 3 wherein the array address lines are fabricated in a single process layer.
5. The capacitor array of claim 1 wherein;
the monotonic combination binary-thermometer coded addressing scheme comprises M+N bits; where,
M bits address M binary coded capacitor groups and N bits address 2 N thermometer coded capacitor groups; such that,
the capacitance of any single thermometer coded capacitor group is greater than (2 M −1) times the nominal capacitance of a unit capacitor and less than (2 M +1) times the nominal capacitance of a unit capacitor.
6. The capacitor array of claim 1 wherein each unit capacitor comprises first and second capacitor plates wherein an electrical connection to the first capacitor plate is made through a hole in the second capacitor plate.
7. The capacitor array of claim 6 wherein the plates are defined in CMOS metal layers.
8. The capacitor array of claim 6 wherein the second capacitor plate further comprises raised sections to provide shielding from adjacent unit capacitors.
9. The capacitor array of claim 8 , wherein the raised sections of each of the plurality of unit capacitors are electrically coupled to the raised sections of their neighbors.
10. The capacitor array of claim 6 wherein each unit capacitor further comprises a third, shielding plate.
11. A frequency reference comprising:
a MEMS resonator with digital signal extraction circuits; and,
a digitally controlled oscillator comprising a capacitor array which comprises a plurality of unit capacitors addressed by a monotonic combination binary—thermometer coded addressing scheme and comprising binary coded capacitor groups and thermometer coded capacitor groups, wherein:
the unit capacitors are arranged in a common-centroid layout,
the binary coded capacitor groups are located closer to the center of the common-centroid layout than the thermometer coded capacitor groups,
each unit capacitor is electrically shielded from one or more neighbor capacitors and from array address lines and,
each unit capacitor comprises two plates wherein an electrical connection to one of the plates is made through a hole in the other.
12. The frequency reference of claim 11 wherein the digital extraction circuits include temperature correction, counting and start-up circuits.
13. A capacitor array comprising:
a plurality of unit capacitors arranged in a common-centroid layout and connected to address lines that connect combinations of capacitors to form an array capacitance according to a digital code, wherein the common-centroid layout comprises binary coded groups of unit capacitors and thermometer coded groups of unit capacitors, wherein:
the binary coded capacitor groups are located closer to the center of the common-centroid layout than the thermometer coded capacitor groups, and the number of bits representing the binary coded capacitor groups is chosen such that a monotonic increase in array capacitance with digital code is achieved.
14. The capacitor array of claim 13 wherein each unit capacitor comprises two plates wherein an electrical connection to one of the plates is made through a hole in the other.
15. The capacitor array of claim 14 wherein each unit capacitor is shielded from its neighbors by raised sections of one of its plates.
16. The capacitor array of claim 13 wherein each unit capacitor is electrically shielded from the address lines.