On-chip jitter testing

1. A method comprising:

providing a clock signal to a circuit under test;

delaying outputs from the circuit under test by different delay values;

comparing, for each delay value, a corresponding output from the circuit under test with a reference signal derived from the clock signal to produce a bit error rate count for each delay value;

representing the bit error rate counts as a cumulative distribution function;

delaying the clock signal by a fixed amount; and

determining a jitter value in the output of the circuit under test based on the bit error rate counts.

2. The method of claim 1 including using a ring oscillator to characterize the different delay values.

3. The method of claim 1 including using a lookup table to determine the jitter value.

4. An apparatus comprising:

an integrated circuit component to provide an output in response to a clock signal, the integrated circuit component including a phase locked loop;

circuitry to delay outputs from the integrated circuit component by different delay values; and

other circuitry to compare the delayed output with a reference signal derived from the clock signal to produce a bit error rate count for each delay value and to determine a jitter value in the integrated circuit component based on the bit error rate counts, wherein the bit error rate counts are represented as a cumulative distribution function.

5. The apparatus of claim 4 including a delay line with a fixed delay value between the clock signal and the other circuitry.

6. The apparatus of claim 4 wherein the other circuitry is to use a lookup table to determine a jitter value.