IP Library Granted Patent US 7,418,528
Granted Patent B2
US 7,418,528 · App. 10/897,130 · Granted Aug 26, 2008

Multimode, multiline data transfer system and method of operating the same

Assignee: Texas Instruments Incorporated
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Quick Facts
Patent No.
US 7,418,528
App. No.
10/897,130
Granted
Aug 26, 2008
Kind
B2
Abstract

Multimode, multiline data transfer systems and methods of operating the same. In one embodiment, one system includes: (1) a bus interface for a bus, the bus interface having a start line driver, a clock line driver and a data line driver and (2) control circuitry coupled to the bus interface and configured to cause the start line driver to establish a selected one of plural data communication protocols over the bus, the clock line driver configured to serve as a further data line driver when the selected one is based on pulse-width modulation.

Claims (30)

1. A multimode, multiline data transfer system, comprising:

a bus interface for a bus, said bus interface having a start line driver, a clock line driver and a data line driver; and

control circuitry coupled to said bus interface and configured to cause said start line driver to establish a selected one of plural data communication protocols over said bus based on a width of a signal on a line driven by said start line driver, said clock line driver configured to serve as a further data line driver when said selected one is based on pulse-width modulation.

2. The system as recited in claim 1 wherein said plural data communication protocols include a standard based on pulse-code modulation, Inter-IC sound, universal serial bus and a standard based on pulse-width modulation.

3. The system as recited in claim 1 wherein said plural data communication protocols include a flex protocol.

4. The system as recited in claim 1 wherein said control circuitry is further configured to cause said start line driver to establish said selected one by asserting a start signal of protocol-dependent duration.

5. The system as recited in claim 1 wherein said bus interface further has a response line driver configured to serve as another data line driver when said selected one is based on said pulse-width modulation.

6. The system as recited in claim 1 wherein said bus interface is selectably configured to operate as a master of said bus.

7. The system as recited in claim 1 wherein said plural data communication protocols include a user-defined protocol.

8. A method of operating a multimode, multiline data transfer system, comprising:

employing a start line driver of a bus interface to establish a selected one of plural data communication protocols over a bus based on a width of a signal on a line driven by said start line driver, said bus interface further having a clock line driver and a data line driver; and

transferring data over said bus according to said selected one, said clock line driver configured to serve as a further data line driver when said selected one is based on pulse-width modulation.

9. The method as recited in claim 8 wherein said plural data communication protocols include a standard based on pulse-code modulation, Inter-IC sound, universal serial bus and a standard based on pulse-width modulation.

10. The method as recited in claim 8 wherein said plural data communication protocols include a flex protocol.

11. The method as recited in claim 8 wherein said employing comprises asserting a start signal of protocol-dependent duration.

12. The method as recited in claim 8 wherein said bus interface further has a response line driver configured to serve as another data line driver when said selected one is based on said pulse-width modulation.

13. The method as recited in claim 8 further comprising causing said bus interface to operate as a master of said bus.

14. The method as recited in claim 8 wherein said plural data communication protocols include a user-defined protocol.

15. A multimode, multiline data transfer system, comprising:

a bus having a start line, a clock line and a data line; and

at least two functional blocks coupled to said bus, each of said at least two functional blocks including:

a bus interface having a start line driver coupled to said start line, a clock line driver coupled to said clock line and a data line driver coupled to said data line, and

control circuitry coupled to said bus interface and configured to cause said start line driver to establish a selected one of plural data communication protocols over said bus based on a width of a signal on said start line, said clock line driver configured to serve as a further data line driver when said selected one is based on pulse-width modulation.

16. The system as recited in claim 15 wherein said plural data communication protocols include a standard based on pulse-code modulation, Inter-IC sound, universal serial bus and a standard based on pulse-width modulation.

17. The system as recited in claim 15 wherein said plural data communication protocols include a flex protocol.

18. The system as recited in claim 15 wherein said control circuitry is further configured to cause said start line driver to establish said selected one by asserting a start signal of protocol-dependent duration.

19. The system as recited in claim 15 wherein said bus interface further has a response line driver configured to serve as another data line driver when said selected one is based on said pulse-width modulation.

20. The system as recited in claim 15 wherein said bus interface is selectably configured to operate as a master of said bus.

21. The system as recited in claim 15 wherein said plural data communication protocols include a user-defined protocol.

22. The system as recited in claim 15 wherein said functional blocks form a portion of a wireless communication device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2004
From: SARDA, VIVEK
To: TEXAS INSTRMENTS INCRORPORATED
Reel/Frame 015613/0726 →
Continuity (1)
Related Publication 20060020733A1 · Jan 26, 2006