Phase-locked loop

1. A phase-locked loop for frequency synthesis having a phase or phase frequency detector, a controllable oscillator, a loop filter, and a frequency divider,

a. the phase-locked loop comprising a reference oscillator or being connectable to a reference oscillator, the reference oscillator being implemented to generate a reference clock signal and output it to a reference input of the phase or phase frequency detector,

b. the controllable oscillator:

(1) having a control input for a control signal and being implemented to generate a clock signal,

(2) having a synthesis frequency adjustable by the control signal applied to the control input in operation, and output it to the frequency divider,

c. the frequency divider being implemented:

(1) to divide the clock signal output by the controllable oscillator by a divider value and thus generate a divider clock signal which has a frequency reduced by the divider value in relation to the synthesis frequency, and

(2) to output the divider clock signal to a feedback input of the phase or phase frequency detector,

d. the phase or phase frequency detector being implemented:

(1) to compare the reference clock signal and the divider clock signal to one another and

(2) to generate a comparison signal which contains information about the phase relation or the frequency relation or about the phase relation and the frequency relation of reference and divider clock signals, and

(3) to output the comparison signal to the loop filter,

e. the loop filter being implemented to generate a control signal, by filtering the comparison signal output by the phase or phase frequency detector, and output it to the controllable oscillator,

characterized in that:

A. the phase-locked loop has a memory for a control value, which is connectable to the control input of the controllable oscillator via a first switch, which is switchable as a function of a first switching signal, and is implemented to output a stored control value, and

B. the frequency divider is connectable at its output via a second switch, which is switchable as a function of a second switching signal, to the reference oscillator.

2. The phase-locked loop according to claim 1 , wherein a reference clock divider is connected downstream from the reference oscillator, which is implemented to generate the reference clock signal by dividing by the reference divider value and output it to the phase or phase frequency detector.

3. The phase-locked loop according to one of claims 1 or 2 , characterized in that the memory is implemented to store and output a digital control value, and the phase-locked loop has a digital/analog converter, which is connected at its input to the memory and at its output to the control input of the controllable oscillator and is implemented to convert a digital control value output by the memory into an analog control value for the controllable oscillator.

4. The phase-locked loop according to claim 3 , characterized in that the phase-locked loop has an analog/digital converter, which is connected or connectable at its input to the control input of the controllable oscillator input and is connected at its output to the memory and is implemented to convert a control value applied to the control input of the controllable oscillator into a digital control value and output it to the memory.

5. The phase-locked loop according to one of claims 1 or 2 , characterized in that the memory is implemented as a sample-and-hold element, to sample a control value applied to the control input of the controllable oscillator, store it, and output it to the control input of the controllable oscillator.

6. The phase-locked loop, according to claim 3 , 4 , or 5 characterized in that the phase-locked loop has two memories, of which a first memory is implemented as a memory for a digital control value and a second memory is implemented as a sample-and-hold element.

7. The phase-locked loop according to one of the preceding claims, characterized by a third switch, switchable as a function of a third switching signal, which is connected between phase or phase frequency detector and controllable oscillator in such a way that the control input of the controllable oscillator is disconnectable from the output of the phase or phase frequency detector.

8. The phase-locked loop according to one of the preceding claims, characterized by a control unit, which is implemented to output a first and a second switching signal, which cause the first and second switches, respectively, to close, upon an initialization signal.

9. The phase-locked loop according to claim 7 or 8 , characterized in that the control unit is implemented to output a third switching signal, which causes the third switch to open, upon the initialization signal.

10. The phase-locked loop according to claim 8 , characterized by a reference clock detector, which is connected to the reference oscillator and is implemented to detect the presence of a valid reference clock signal and to signal the control unit by a PLL start signal.

11. The phase-locked loop according to claim 10 , characterized in that the control unit is implemented to output a first and a second switching signal, which cause the first and second switches, respectively, to open, upon receiving the PLL start signal.

12. The phase-locked loop according to claim 9 or 11 , characterized in that the control unit is implemented to output a third switching signal, which causes the third switch to close, upon receiving the PLL start signal.

13. The phase-locked loop according to one of the preceding claims, characterized in that the memory is implemented to output a series of different control values.

14. An electromechanical implant, particularly a cardiac pacemaker, defibrillator, or cardioverter, having a telemetry unit for transmitting data from the implant to an external device, characterized in that the telemetry unit comprises a phase-locked loop according to one of the preceding claims for generating a transmit or receive clock pulse.