Non-volatile memory and method with improved sensing
View Patent ↗A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.
1. A non-volatile memory, comprising:
an array of memory storage units;
a plurality of sense amplifiers for sensing a group of memory storage units in parallel;
each of said plurality of sense amplifiers having properties dependent on operating environment and a set of control signals; and
a reference circuit having elements with properties representative of said plurality of sense amplifiers and sharing a common operating environment with said plurality of sense amplifiers, said reference circuit, responsive to said elements operating in the operating environment, generating said set of control signals such that said plurality of sense amplifiers are controlled to have its properties substantially insensitive to the operating environment and
each sense amplifier further comprising:
a discriminator coupled to receive a conduction current of an associated memory cell, said discriminator discriminating whether the conduction current is higher or lower than a predetermined demarcation current value;
a latch being set to register the associated memory cell in response to said discriminator identifying a conduction current higher than said predetermined demarcation current value; and
an inhibitor responsive to said latch being set to turn off the conduction current of the associated memory cell.
2. The non-volatile memory of claim 1 , wherein said properties include a threshold voltage of a component transistor.
3. The non-volatile memory of claim 1 , wherein said properties include a capacitance of a component capacitor.
4. The non-volatile memory of claim 1 , wherein said operating environment includes a given power supply.
5. The non-volatile memory of claim 1 , wherein said operating environment includes a given temperature.
6. The non-volatile memory of claim 1 , wherein said set of control signals includes a timing signal calibrated to a reference current.
7. The non-volatile memory of claim 1 , wherein said set of control signals includes a voltage for controlling a voltage clamp.
8. A non-volatile memory, comprising:
a plurality of sense amplifiers for sensing a group of memory storage units in parallel, each of said plurality of sense amplifiers having properties dependent on operating environment and a set of control signals;
a reference circuit having elements with properties representative of a typical member of said plurality of sense amplifiers and located in a common operating environment with said plurality of sense amplifiers; and
means for generating said set of control signals, responsive to said elements operating in the operating environment such that said plurality of sense amplifiers is controlled to have its properties substantially insensitive to the operating environment and each sense amplifier further comprising:
a discriminator coupled to receive a conduction current of an associated memory cell, said discriminator discriminating whether the conduction current is higher or lower than a predetennined demarcation current value;
a latch being set to register the associated memory cell in response to said discriminator identifying a conduction current higher than said predetennined demarcation current value; and
an inhibitor responsive to said latch being set to turn off the conduction current of the associated memory cell.
9. The method as in any one of claims 1 - 8 , wherein:
each memory storage unit one bit of data.
10. The method as in any one of claims 1 - 8 , wherein:
each memory storage unit stores more than one bit of data.
11. A method of controlling a plurality of sensing circuits for a non-volatile memory, comprising:
providing a predetermined demarcation current value to discriminate between two memory states;
sensing the plurality of memory cells in parallel to identify those memory cells having conduction currents higher than said predetermined demarcation current value;
inhibiting the conduction currents of those higher current memory cells after identifying all those higher current memory cells among said plurality of memory cells being sensed in parallel;
wherein said sensing further comprises:
providing a plurality of sense amplifiers for sensing a group of memory storage units in parallel, each of said plurality of sense amplifiers having properties dependent on operating environment and a set of control signals;
locating a reference circuit having elements with properties representative of a typical member of said plurality of sense amplifiers in a common operating environment with said plurality of sense amplifiers; and
generating said set of control signals, responsive to said elements operating in the operating environment such that said plurality of sense amplifiers is controlled to have its properties substantially insensitive to the operating environment.
12. The method as in claim 11 , wherein:
said plurality of memory storage units is flash EEPROM.
13. The method as in any one of claims 11 - 12 , wherein:
each memory storage unit one bit of data.
14. The method as in any one of claims 11 - 12 , wherein:
each memory storage unit stores more than one bit of data.