IP Library Granted Patent US 7,429,784
Granted Patent B2
US 7,429,784 · App. 11/627,237 · Granted Sep 30, 2008

Package structure

Assignee: Advanced Semiconductor Engineering, Inc.
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Quick Facts
Patent No.
US 7,429,784
App. No.
11/627,237
Granted
Sep 30, 2008
Kind
B2
Abstract

A package structure is provided herein. The package structure includes a first substrate and a second substrate. A first seal ring having a first height is disposed around a predetermined area of the first substrate and between the first and second substrates. A second seal ring having a second height is disposed on the first substrate and around the first seal ring. A sealant is provided between the first and second seal rings to seal up the package structure.

Claims (24)

1. A package structure, comprising:

a first substrate having an upper surface, the upper surface of the first substrate defining a predetermined area;

a second substrate having a lower surface, disposed above the first substrate;

a first seal ring having a first height, disposed on the upper surface of the first substrate and around the periphery of the predetermined area, the first seal ring connecting with the lower surface of the second substrate;

a second seal ring having a second height smaller than the first height, disposed on the upper surface of the first substrate and around the first seal ring, wherein the area enclosed between the first and second seal rings defines a channel; and

a sealant disposed in the channel.

2. The package structure as claimed in claim 1 , further comprising:

at least one device disposed on the predetermined area.

3. The package structure as claimed in claim 2 , wherein the second substrate is transparent.

4. The package structure as claimed in claim 2 , wherein the second substrate is a glass substrate.

5. A package structure, comprising:

a first substrate having an upper surface, the upper surface of the first substrate defining a predetermined area;

a second substrate having a lower surface, disposed above the first substrate;

a first seal ring having a first height, disposed on the upper surface of the first substrate and around the periphery of the predetermined area, the first seal ring connecting with the lower surface of the second substrate;

a second seal ring having a second height smaller than the first height, disposed on the upper surface of the first substrate and around the first seal ring, wherein the area enclosed between the first and second seal rings defines a channel;

a third seal ring having a third height, disposed on the lower surface of the second substrate and corresponding to the channel; and

a sealant disposed in the channel.

6. The package structure as claimed in claim 5 , wherein the third height is smaller than the first height.

7. The package structure as claimed in claim 5 , further comprising:

at least one device disposed on the predetermined area.

8. The package structure as claimed in claim 7 , wherein the second substrate is transparent.

9. The package structure as claimed in claim 7 , wherein the second substrate is a glass substrate.

10. The package structure as claimed in claim 2 , wherein the device is selected from the group consisting of semiconductor device, MEMS device and optoelectronic device.

11. The package structure as claimed in claim 7 , wherein the device is selected from the group consisting of semiconductor device, MEMS device and optoelectronic device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2007
From: HUANG, CHENG WEI
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 018805/0985 →
Priority Claims (1)
TW 95110365 A · Mar 24, 2006 · national
Continuity (1)
Related Publication 20070222048A1 · Sep 27, 2007