Semiconductor memory device

1. A semiconductor memory device arranged to perform a refreshing operation to holding data, comprising:

a temperature detector circuit configured to output a temperature signal;

a reference temperature signal output circuit configured to output at least one reference temperature signal from a plurality of different reference temperatures signals to be compared with said temperature signal;

a temperature comparator circuit configured to compare said temperature signal with said reference temperature signal; and

an oscillator circuit configured to change a refresh frequency according to the output signal of said temperature comparator circuit,

wherein the at least one reference temperature signal is selected based on the output signal of said temperature comparator circuit.

2. The semiconductor memory device according to claim 1 , wherein said oscillator circuit changes said refresh frequency higher at higher temperature and changes said refresh frequency lower at lower temperature.

3. The semiconductor memory device according to claim 1 , wherein the oscillator circuit includes a frequency divider configured to change the refresh frequency.

4. A semiconductor memory device comprising:

a reference temperature signal output circuit for outputting a reference temperature signal from a plurality of reference temperature signals corresponding to a plurality of different temperature;

a temperature comparator circuit for comparing a temperature signal with said reference temperature signal, the temperature signal indicating a temperature of the semiconductor memory device; and

a refresh period control circuit for changing a refresh frequency according to the output signal of said temperature comparator circuit,

wherein the reference temperature signal is selected from the plurality of reference temperature signals based on the output signal of said temperature comparator circuit.

5. The semiconductor memory device according to claim 4 , further comprising:

a temperature detector circuit for outputting the temperature signal.

6. The semiconductor memory device according to claim 4 , further comprising:

a selection signal output circuit for outputting a selection signal selecting the reference temperature signal according to the output of said temperature comparator circuit.

7. The semiconductor memory device according to claim 4 , wherein the refresh period control circuit includes an oscillator configured to output a oscillating signal, a refresh signal having the refresh frequency is generated based on the oscillating signal.

8. A semiconductor memory device performing a refresh operation, comprising:

a temperature detector circuit configured to output a temperature signal,

wherein the temperature signal is compared with at least one of a plurality of reference voltage temperature signals and a refresh frequency which determines a interval between the refresh operation is changed by the compared result, the plurality of reference voltage temperature signals corresponding to a plurality of different temperature, and

wherein the at least one reference temperature signal is selected based on the compared result.

9. The semiconductor memory device according to claim 8 , further comprising:

an oscillator circuit configured to generate an oscillating signal which is a basis of a refresh signal having the refresh frequency.

10. The semiconductor memory device according to claim 8 , wherein the temperature detector circuit is configured to be controlled by a temperature detection enable signal.

11. A semiconductor memory device arranged to perform a refreshing operation to holding data, comprising:

a temperature detector circuit configured to output a temperature signal;

a reference temperature signal output circuit configured to output a single reference temperature signal from a plurality of different reference temperatures signals to be compared with said temperature signal;

a temperature comparator circuit configured to compare said temperature signal with said single reference temperature signal; and

an oscillator circuit configured to change a refresh frequency according to the output signal of said temperature comparator circuit,

wherein the temperature comparator includes a single differential amplifier for comparing said temperature signal with said single reference temperature signal.

12. The semiconductor memory device according to claim 11 , wherein said oscillator circuit changes said refresh frequency higher at higher temperature and changes said refresh frequency lower at lower temperature.

13. The semiconductor memory device according to claim 11 , wherein the oscillator circuit includes a frequency divider configured to change the refresh frequency.

14. The semiconductor memory device according to claim 11 , wherein the single reference temperature signal is selected based on the output signal of said temperature comparator circuit.

15. The semiconductor memory device according to claim 11 , wherein the single differential amplifier is activated by a temperature detection enable signal.

16. The semiconductor memory device according to claim 11 , further comprising:

a first latch circuit configured to latch the compared signal output by the single differential amplifier.

17. The semiconductor memory device according to claim 16 , wherein the first latch circuit outputs the latched signal based on a starter signal.

18. The semiconductor memory device according to claim 11 , further comprising:

a plurality of second latch circuits configured to latch the output signal of said temperature comparator circuit.

19. The semiconductor memory device according to claim 18 , wherein the plurality of the second latch circuits output the latched signal to the oscillator circuit.

20. The semiconductor memory device according to claim 18 , wherein the plurality of the second latch circuits operate based on the output signal of said temperature comparator circuit.