Multi-interfaced memory

1. An apparatus comprising:

an array of memory cells;

first interface circuitry to provide access to the array;

second interface circuitry to provide access to the array; and

a data bus;

wherein the first interface circuitry and the second interface circuitry share the data bus;

wherein the first interface circuitry comprises a random access memory interface and the second interface circuitry comprises a paged access memory interface; and

wherein the first interface circuitry is configured to provide deterministic initial access latency and the second interface circuitry is configured to allow variable initial access latency.

2. The apparatus as recited in claim 1 , wherein the array of memory cells comprises flash memory cells.

3. The apparatus as recited in claim 1 , wherein the first interface circuitry is configured to access random memory locations and the second interface circuitry is configured to access page memory locations.

4. The apparatus as recited in claim 1 , wherein the first interface circuitry and the second interface circuitry access the memory cells in different quantities.

5. The apparatus as recited in claim 1 , wherein the first interface circuitry and the second interface circuitry access the memory cells in a different way.

6. The apparatus as recited in claim 1 , wherein each of the first interface circuitry and the second interface circuitry are capable of accessing the entire array of memory cells.

7. The apparatus as recited in claim 6 , wherein accessing the entire array comprises reading and writing the entire array.

8. The apparatus as recited in claim 1 , wherein the first interface circuitry and the second interface circuitry each have an enable signal.

9. The apparatus as recited in claim 1 , wherein the array of memory cells comprises phase change memory cells.

10. The apparatus as recited in claim 1 , wherein the array of memory cells comprises magnetic memory cells.

11. A method comprising:

receiving a memory access request having an address;

decoding the address; and

enabling one of a first interface and a second interface to a memory based on results of the decoding the address, the first interface comprising a random access memory interface and the second interface is a paged access memory interface, wherein the first interface is configured to provide deterministic initial access latency and the second interface is configured to allow variable initial access latency.

12. The method as recited in claim 11 , wherein the enabling one of the first interface and the second interface comprises activating a first enable signal or a second enable signal.

13. The method as recited in claim 11 , wherein the first interface is configured to access random memory locations and the second interface is configured to access block memory locations.