IP Library Granted Patent US 7,473,988
Granted Patent B2
US 7,473,988 · App. 11/513,249 · Granted Jan 6, 2009

Wiring board construction including embedded ceramic capacitors(s)

Assignee: NGK Spark Plug Co., Ltd
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Quick Facts
Patent No.
US 7,473,988
App. No.
11/513,249
Granted
Jan 6, 2009
Kind
B2
Abstract

A wiring board includes a substrate core, ceramic capacitors and a built-up layer. The substrate core has a housing opening portion therein which opens at a core main surface. The ceramic capacitors are accommodated in the housing opening portion and oriented such that the core main surface and a capacitor main surface of each capacitor face the same way. The built-up layer includes semiconductor integrated circuit element mounting areas at various locations on a surface thereof. In the substrate core, each ceramic capacitor is respectively disposed in an area corresponding to each semiconductor integrated circuit element mounting area.

Claims (38)

1. A wiring board comprising:

a substrate core including a core main surface and a core rear surface;

a plurality of ceramic capacitors each including a capacitor main surface and comprising an alternatively laminated structure including a first inner electrode layer and a second inner electrode layer which sandwich a ceramic dielectric layer therebetween, said ceramic capacitors being embedded in said substrate core and being oriented such that said core main surface and said capacitor main surface face in a common direction; and

a built-up layer having a laminated structure wherein at least one interlayer insulating layer and at least one conductor layer are alternately laminated on said core main surface and said capacitor main surface, said built-up layer including a plurality of semiconductor integrated circuit element mounting areas at different locations on a surface of said built-up layer, and

said plurality of ceramic capacitors being disposed in areas of said substrate core corresponding to said plurality of semiconductor integrated circuit element mounting areas,

said substrate core including a plurality of housing opening portions therein which open at said core main surface, and

said ceramic capacitors being respectively accommodated in said plurality of housing opening portions and being oriented such that said core main surface and said capacitor main surface face in a common direction,

said substrate core further including a conductor portion which electrically connects said core main surface side and said core rear surface side and which is disposed in an area formed between said adjacent housing opening portions.

2. A wiring board according to claim 1 ,

wherein said semiconductor integrated circuit element mounting area has a dimension no greater than the corresponding dimension of said capacitor main surface of the corresponding ceramic capacitor, and

wherein said at least one semiconductor integrated circuit element mounting area is located within said capacitor main surface of the corresponding ceramic capacitor, as viewed in the thickness direction of said ceramic capacitor.

3. A wiring board according to claim 1 ,

wherein the dimensions of at least one said semiconductor integrated circuit element mounting area are between about 50% and 90% of the dimensions of said capacitor main surface of the corresponding ceramic capacitor.

4. A wiring board according to claim 1 ,

wherein said built-up layer comprises a first built-up layer and

wherein said wiring board includes a second built-up layer having an alternately laminated structure wherein at least one interlayer insulating layer and at least one conductor layer are alternately laminated on said core rear surface and said capacitor rear surface.

5. A wiring board according to claim 1 ,

wherein at least one of said ceramic capacitors includes a side face dummy electrode facing an adjoining ceramic capacitor of said plurality of ceramic capacitors.

6. A wiring board according to claim 5 , further comprising a conductor layer serving as ground in a built-up layer, and

wherein said side face dummy electrode is electrically connected to said conductor layer.

7. A wiring board comprising:

a substrate core including a core main surface and a core rear surface;

a plurality of ceramic capacitors each including a capacitor main surface and comprising an alternatively laminated structure including a first inner electrode layer and a second inner electrode layer which sandwich a ceramic dielectric layer therebetween, said ceramic capacitors being embedded in said substrate core and being oriented such that said core main surface and said capacitor main surface face in a common direction; and

a built-up layer having a laminated structure wherein at least one interlayer insulating layer and at least one conductor layer are alternately laminated on said core main surface and said capacitor main surface, said built-up layer including a plurality of semiconductor integrated circuit element mounting areas at different locations on a surface of said built-up layer, and

said plurality of ceramic capacitors being disposed in areas of said substrate core corresponding to said plurality of semiconductor integrated circuit element mounting areas,

wherein said substrate core includes a housing opening portion therein which opens at said core main surface, and

wherein said ceramic capacitors are accommodated in said housing opening portion and are oriented such that said core main surface and said capacitor main surface face in a common direction,

said wiring board further comprising a filler filling an area formed between adjacent ceramic capacitors, and a conductor portion, formed in said filler, for electrically connecting said core main surface side and said core rear surface side.

8. A wiring board according to claim 7 ,

wherein said semiconductor integrated circuit element mounting area has a dimension no greater than the corresponding dimension of said capacitor main surface of the corresponding ceramic capacitor, and

wherein said at least one semiconductor integrated circuit element mounting area is located within said capacitor main surface of the corresponding ceramic capacitor, as viewed in the thickness direction of said ceramic capacitor.

9. A wiring board according to claim 7 ,

wherein the dimensions of at least one said semiconductor integrated circuit element mounting area are between about 50% and 90% of the dimensions of said capacitor main surface of the corresponding ceramic capacitor.

10. A wiring board according to claim 7 ,

wherein said built-up layer comprises a first built-up layer and

wherein said wiring board includes a second built-up layer having an alternately laminated structure wherein at least one interlayer insulating layer and at least one conductor layer are alternately laminated on said core rear surface and said capacitor rear surface.

11. A wiring board according to claim 7 ,

wherein at least one of said ceramic capacitors includes a side face dummy electrode facing an adjoining ceramic capacitor of said plurality of ceramic capacitors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2006
From: URASHIMA, KAZUHIRO; YURI, SHINJI; SATO, MANABU; OTSUKA, JUN
To: NGK SPARK PLUG CO., LTD
Reel/Frame 018742/0806 →
Priority Claims (2)
JP 2005-254029 · Sep 1, 2005 · national
JP 2006-198796 · Jul 20, 2006 · national
Continuity (1)
Related Publication 20070045815A1 · Mar 1, 2007