Clock supply circuit and method
An object is to provide a clock supply circuit capable of supplying a clock signal with a short oscillation stabilization waiting time. There is provided a clock supply circuit having a filter removing from a first clock signal pulses having a shorter pulse width than a threshold value and passing pulses having a longer pulse width than the threshold value to thereby output a second clock signal; and a divider dividing the second clock signal to thereby output a third clock signal.
1. A clock supply circuit, comprising:
a filter for removing pulses having a shorter pulse width than a threshold value from a first clock signal pulses and passing pulses having a longer pulse width than the threshold value to output a second clock signal;
a divider dividing the second clock signal to output a third clock signal; and
a clock output unit outputting the first clock signal as a fourth clock signal without change or generating and outputting a fourth clock signal based on the first clock signal, wherein the fourth clock signal is generated based on the first clock signal without having the first clock signal pass through the filter,
wherein a frequency of the fourth clock signal is a higher frequency than a frequency of the third clock signal.
2. The clock supply circuit according to claim 1 , further comprising:
selector selecting and outputting the third clock signal or the fourth clock signal.
3. The clock supply circuit according to claim 2 ,
wherein said selector selects and outputs the third clock signal until a count value of a counter reaches a first count value, and selects and outputs the fourth clock signal after the first count value is reached.
4. The clock supply circuit according to claim 2 , further comprising:
an enable signal generating circuit generating a first enable signal indicating that the third clock signal is usable and a second enable signal indicating that the fourth clock signal is usable,
wherein the third clock signal becomes usable earlier than the fourth clock signal.
5. The clock supply circuit according to claim 4 , further comprising:
a power supply voltage monitoring circuit monitoring stability of a power supply voltage after a start-up,
wherein said enable signal generating circuit generates the first and second enable signals indicating that the third and fourth clock signals are usable after the power supply voltage becomes stable.
6. The clock supply circuit according to claim 4 ,
wherein a clock signal outputted by said selector and the first enable signal are supplied to a first circuit, and the fourth clock signal and the second enable signal are supplied to a second circuit.
7. A clock supply method, comprising:
a filtering step of removing pulses having a shorter pulse width than a threshold value from a first clock signal and passing pulses having a longer pulse width than the threshold value to output a second clock signal;
a dividing step of dividing the second clock signal to output a third clock signal; and
a clock outputting step of outputting the first clock signal as a fourth clock signal without change or generating and outputting a fourth clock signal based on the first clock signal, wherein the fourth clock signal is generated based on the first clock signal without filtering the first clock signal,
wherein a frequency of the fourth clock signal is a higher frequency than a frequency of the third clock signal.
8. The clock supply method according to claim 7 , further comprising:
a selecting step of selecting and outputting the third clock signal or the fourth clock signal.
9. The clock supply method according to claim 8 ,
wherein said selecting step selects and outputs the third clock signal until a count value of a counter reaches a first count value, and selects and outputs the fourth clock signal after the first count value is reached.
10. The clock supply method according to claim 8 , further comprising:
an enable signal generating step of generating a first enable signal indicating that the third clock signal is usable and a second enable signal indicating that the fourth clock signal is usable,
wherein the third clock signal becomes usable earlier than the fourth clock signal.
11. The clock supply method according to claim 10 ,
wherein said enable signal generating step generates the first and second enable signals indicating that the third and fourth clock signals are usable after a power supply voltage becomes stable after a start-up.
12. The clock supply method according to claim 10 ,
wherein a clock signal selected and outputted by said selecting step and the first enable signal are supplied to a first circuit, and the fourth clock signal and the second enable signal are supplied to a second circuit.