IP Library Granted Patent US 7,518,441
Granted Patent B2
US 7,518,441 · App. 11/534,860 · Granted Apr 14, 2009

Signal processor for use with a power amplifier in a wireless circuit

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,518,441
App. No.
11/534,860
Granted
Apr 14, 2009
Kind
B2
Abstract

A signal processor has an input terminal and an output terminal for use in a wireless transmitter, for generating a radio frequency signal suitable for transmission, either with or without further power amplification. The signal processor separates an input signal into first and second processing paths, the first processing path generating a pulse train signal which is a digitised envelope signal, and the second processing path comprising phase processing means operable to generate a constant envelope phase signal. An RF switch is operable to switch the phase signal by means of the pulse train signal.

Claims (20)

1. A signal processor for use in a wireless transmitter, for generating a radio frequency signal suitable for transmission, either with or without further power amplification, the signal processor comprising signal separating means for separating an input signal into first and second processing paths, the first processing path comprising signal envelope processing means for generating a pulse train signal being a digitized envelope signal, and the second processing path comprising phase processing means operable to generate a constant envelope phase signal, and further comprising an RF switch operable to switch said phase signal by means of said pulse train signal, and further comprising a digital signal processor implementing said envelope processing means, said phase processing means and said RF switch.

2. A signal processor in accordance with claim 1 , wherein said signal separating means comprises an input terminal and at least a first output terminal and a second output terminal.

3. A signal processor in accordance with claim 2 , wherein said first and second output terminals are connected to said first and second processing paths respectively.

4. A signal processor in accordance with claim 1 , wherein said envelope processing means comprises an input terminal and an output terminal.

5. A signal processor in accordance with claim 4 , wherein said input terminal of said envelope processing means is connected with said first output terminal of said signal separating means.

6. A signal processor in accordance with claim 1 , wherein said signal envelope processing means further comprises an envelope detecting means for generating an envelope signal, and an envelope digitizing means for generating said pulse train signal.

7. A signal processor in accordance with claim 6 , wherein said envelope detecting means comprises an input terminal and an output terminal, and said input terminal of said envelope detecting means is the input terminal of said envelope processing means.

8. A signal processor in accordance with claim 7 , wherein said envelope digitizing means comprises an input terminal and an output terminal, and said output terminal of said envelope detecting means is the output terminal of said envelope processing means.

9. A signal processor in accordance with claim 8 , wherein the output terminal of said envelope detecting means is connected to the input terminal of said envelope digitizing means.

10. A signal processor in accordance with claim 1 , wherein said RF switch comprises an input terminal, an output terminal and a control terminal.

11. A signal processor in accordance with claim 10 , wherein said output terminal of said RF switch is the output terminal of said signal processor.

12. A signal processor in accordance with claim 10 , wherein an output terminal of said envelope processing means is connected to said control terminal of said RF switch.

13. A signal processor in accordance with claim 1 , wherein said phase processing means comprises an input terminal and an output terminal.

14. A signal processor in accordance with claim 13 wherein said input terminal of said phase processing means is connected to a second output terminal of said signal separating means and said output terminal of said phase processing means is connected to an input terminal of said RF switch.

15. A method of processing an input signal for generating a radio frequency signal suitable for transmission, the method comprising the steps of

generating a pulse train signal from said input signal, said pulse train signal being a digitized envelope signal;

generating a constant envelope phase signal from said input signal; and

RF switching said constant envelope phase signal by means of said pulse train signal,

wherein a digital signal processor implements the steps of generating a constant envelope phase signal from said input signal and RF switching said constant envelope phase signal by means of said pulse train signal.

16. A method in accordance with claim 15 , wherein said step of generating an envelope signal further comprises the step of detecting the envelope of said input signal and digitizing said detected input envelope signal.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 018879 FRAME 0839. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 28, 2007
From: NESIMOGLU, TAYFUN; MORRIS, KEVIN A.
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 018941/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2007
From: NESIMOGLU, TAYFUN; MORIS, KEVIN A
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 018879/0839 →
Priority Claims (1)
GB 0524426.4 · Nov 30, 2005 · national
Continuity (1)
Related Publication 20070123184A1 · May 31, 2007