IP Library Granted Patent US 7,519,752
Granted Patent B2
US 7,519,752 · App. 11/348,968 · Granted Apr 14, 2009

Apparatus for using information and a count in reissuing commands requiring access to a bus and methods of using the same

Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 7,519,752
App. No.
11/348,968
Granted
Apr 14, 2009
Kind
B2
Abstract

In a first aspect, a first method of reissuing a command involving bus access is provided. The first method includes the steps of (1) storing information associated with commands that are to be reissued, wherein the commands are each associated with respective input/output (I/O) devices seeking bus access; (2) storing a count for each of the commands, each count indicating a number of times the associated command has been reissued; (3) selecting a command to be reissued, from among the commands, based on the information associated with the command; and (4) determining a delay after which the selected command will be reissued, wherein the delay is determined based on the count associated with the selected command. Numerous other aspects are provided.

Claims (69)

1. A method of reissuing a command involving bus access, the method comprising:

storing information associated with commands that are to be reissued, wherein the commands are each associated with respective input/output (I/O) devices seeking bus access;

storing a count for each of the commands, each count indicating a number of times the associated command has been reissued;

selecting a command to be reissued, from among the commands, based on the information associated with the command; and

determining a delay after which the selected command will be reissued, wherein the delay is determined based on the count associated with the selected command.

2. The method of claim 1 wherein:

storing information associated with commands that are to be reissued includes storing information associated with commands that are to be reissued in a register; and

storing a count for each of the commands includes storing a count for each of the commands in an array.

3. The method of claim 1 further comprising reissuing the selected command after waiting the delay.

4. The method of claim 1 further comprising incrementing the count associated with the selected command.

5. The method of claim 1 wherein determining the delay after which the selected command will be reissued includes employing the same logic to determine a delay for any selected command.

6. The method of claim 1 wherein selecting the command includes selecting the command based on a previous command selected by selecting information associated with the previous command.

7. The method of claim 1 wherein determining the delay after which the selected command will be reissued includes:

generating a random number;

generating the delay based on the random number and the count associated with the selected command;

wherein the same logic is employed to generate the delay for any selected command.

8. The method of claim 2 wherein selecting the command includes selecting the command based on a predetermined bit position of the register.

9. The method of claim 3 further comprising resetting the count associated with the reissued command when the reissued command completes.

10. The method of claim 3 further comprising storing information associated with the reissued command again if the reissued command is to be reissued again.

11. The method of claim 7 wherein determining the delay based on the random number and the count associated with the selected command includes:

determining a predetermined portion of the random number to employ to generate the delay; and

employing the predetermined portion of the random number to generate the delay.

12. An apparatus for reissuing a command involving bus access, comprising:

command reissuing logic having:

a register; and

an array coupled to the register;

the command reissuing logic is adapted to:

store information associated with commands that are to be reissued, wherein the commands are each associated with respective input/output (I/O) devices seeking bus access;

store a count for each of the commands, each count indicating a number of times the associated command has been reissued;

select a command to be reissued, from among the commands, based on the information associated with the command; and

determine a delay after which the selected command will be reissued, wherein the delay is determined based on the count associated with the selected command.

13. The apparatus of claim 12 wherein the command reissuing logic is further adapted to:

store information associated with commands that are to be reissued in the register; and

store a count for each of the commands in the array.

14. The apparatus of claim 12 wherein the command reissuing logic is further adapted to reissue the selected command after waiting the delay.

15. The apparatus of claim 12 wherein the command reissuing logic is further adapted to increment the count associated with the selected command.

16. The apparatus of claim 12 wherein the command reissuing logic is further adapted to employ the same logic to determine a delay for any selected command.

17. The apparatus of claim 12 wherein the command reissuing logic is further adapted to select the command based on a previous command selected by selecting information associated with the previous command.

18. The apparatus of claim 12 wherein:

the command reissuing logic further includes a shift register adapted to generate a random number;

the command reissuing logic is further adapted to generate the delay based on the random number and the count associated with the selected command; and

the same register, array and shift register are employed to generate the delay for any selected command.

19. The apparatus of claim 13 wherein the command reissuing logic is further adapted to select the command based on a predetermined bit position of the register.

20. The apparatus of claim 11 wherein the command reissuing logic is further adapted to reset the count associated with the reissued command when the reissued command completes.

21. The apparatus of claim 11 wherein the command reissuing logic is further adapted to store information associated with the reissued command again if the reissued command is to be reissued again.

22. The apparatus of claim 18 wherein the command reissuing logic is further adapted to:

determine a predetermined portion of the random number to employ to generate the delay; and

employ the predetermined portion of the random number to generate the delay.

23. A system, comprising:

a processor;

a plurality of input/output (I/O) devices;

a bus, coupled to the I/O devices and the processor, and adapted to receive commands from the I/O devices and the processor; and

an apparatus for reissuing a command involving bus access including:

command reissuing logic having:

a register; and

an array coupled to the register;

the command reissuing logic is adapted to:

store information associated with commands that are to be reissued, wherein the commands are each associated with respective input/output (I/O) devices seeking bus access;

store a count for each of the commands, each count indicating a number of times the associated command has been reissued;

select a command to be reissued, from among the commands, based on the information associated with the command; and

determine a delay after which the selected command will be reissued, wherein the delay is determined based on the count associated with the selected command.

24. The system of claim 23 wherein the command reissuing logic is further adapted to:

store information associated with commands that are to be reissued in the register; and

store a count for each of the commands includes storing a count for each of the commands in the array.

25. The system of claim 23 wherein the command reissuing logic is further adapted to:

reissue the selected command after waiting the delay; and

at least one of:

reset the count associated with the reissued command when the reissued command completes; and

store information associated with the reissued command in the register again if the reissued command is to be reissued again.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2006
From: HANDLOGTEN, GLEN H.; NORGAARD, DAVID A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 017271/0901 →
Continuity (1)
Related Publication 20070186012A1 · Aug 9, 2007