IP Library Granted Patent US 7,546,480
Granted Patent B1
US 7,546,480 · App. 11/951,672 · Granted Jun 9, 2009

High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements

Assignee: Extreme Networks, Inc.
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Quick Facts
Patent No.
US 7,546,480
App. No.
11/951,672
Granted
Jun 9, 2009
Kind
B1
Abstract

In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described. The invention is directed to a system for detecting either or both underflow and overflow of a circular buffer capable of holding n entries. The invention is also directed to a method of detecting either or both underflow and overflow of a circular buffer capable of holding n entries.

Claims (20)

1. A system for detecting either or both underflow and overflow of a circular buffer capable of holding n entries, wherein n is an integer of two or more, each entry including a tag portion, the system comprising:

a first counter for circularly counting through m values, wherein m is an integer less than n and is not evenly divisible into n; and

first logic for performing a read operation by (1) reading an entry from the buffer, (2) comparing the tag portion of the entry with the contents of the counter, (3) either or both (a) signaling an underflow condition if the tag portion of the entry is less than the contents of the counter, and (b) signaling an overflow condition if the tag portion of the entry exceeds the contents of the counter, and (4) otherwise updating the contents of the first counter to reflect the read operation.

2. The system of claim 1 , further comprising:

a second counter for circularly counting through m values; and

second logic for performing a write operation by (1) forming an entry to be written to the buffer, the tag portion of the entry representative of the contents of the second counter, (2) writing the entry to the buffer, and (3) updating the contents of the second counter to reflect the write operation.

3. The system of claim 2 , wherein the first logic is configured to update the contents of the first counter during a read operation by incrementing it, and the second logic is configured to update the contents of the second counter during a write operation by incrementing it.

4. The system of claim 2 , wherein the first logic is configured to update the contents of the first counter during a read wherein the first logic is configured to update the contents of the first counter during a read operation by decrementing it, and the second logic is configured to update the contents of the second counter during a write operation by decrementing it.

5. A method of detecting either or both underflow and overflow of a circular buffer capable of holding n entries, wherein n is an integer of two or more, each entry including a tag portion, the method comprising performing a read operation by:

reading an entry from the buffer;

comparing the tag portion of the entry with the contents of a first counter configured to circularly count through m values, where m is an integer less than n and not evenly divisible into n;

either or both (a) signaling an underflow condition if the tag portion of the entry is less than the contents of the first counter, and (b) signaling an overflow condition if the tag portion of the entry is greater than the contents of the first counter; and

updating the contents of the first counter if the contents of the first counter equal the tag portion of the entry.

6. The method of claim 5 , further comprising performing a write operation by:

forming an entry to be written to the buffer, the tag portion of the entry representative of the contents of a second counter configured to circularly count through m values;

writing the entry to the buffer; and

updating the contents of the second counter.

7. The method of claim 6 , wherein the step of updating the contents of the first counter during a read operation comprises incrementing it, and the step of updating the contents of the second counter during a write operation comprises incrementing it.

8. The method of claim 6 , wherein the step of updating the contents of the first counter during a read operation comprises decrementing it, and the step of updating the contents of the second counter during a write operation comprises decrementing it.

9. The method of claim 5 , wherein the circular buffer is a FIFO buffer.

Assignments (7)
RELEASE OF PATENT AND TRADEMARK SECURITY INTEREST AT REEL/FRAME NO. 46050/0546 Recorded Jul 30, 2026
From: BANK OF MONTREAL, AS AGENT
To: EXTREME NETWORKS, INC.
Reel/Frame 076081/0088 →
RELEASE OF SECURITY INTEREST Recorded May 1, 2018
From: SILICON VALLEY BANK
To: EXTREME NETWORKS, INC.
Reel/Frame 046051/0775 →
SECURITY INTEREST Recorded May 1, 2018
From: EXTREME NETWORKS, INC.
To: BANK OF MONTREAL
Reel/Frame 046050/0546 →
THIRD AMENDED AND RESTATED PATENT AND TRADEMARK SECURITY AGREEMENT Recorded Oct 31, 2017
From: EXTREME NETWORKS, INC.
To: SILICON VALLEY BANK
Reel/Frame 044639/0300 →
SECOND AMENDED AND RESTATED PATENT AND TRADEMARK SECURITY AGREEMENT Recorded Jul 14, 2017
From: EXTREME NETWORKS, INC.
To: SILICON VALLEY BANK
Reel/Frame 043200/0614 →
AMENDED AND RESTATED PATENT AND TRADEMARK SECURITY AGREEMENT Recorded Oct 31, 2016
From: EXTREME NETWORKS, INC.
To: SILICON VALLEY BANK
Reel/Frame 040521/0762 →
SECURITY AGREEMENT Recorded Jul 27, 2015
From: EXTREME NETWORKS, INC.
To: SILICON VALLEY BANK
Reel/Frame 036189/0284 →
Continuity (1)
Division 1040596100 · Apr 1, 2003