Bottom source LDMOSFET structure and method
This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.
1. A bottom-source lateral diffusion MOS (BS-LDMOS) device comprising a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between said source region and a drain region, said BS-LDMOS further comprising:
a combined sinker-channel region formed as a single diffusion region having a dopant profile diffused from a deep implant for controlling a cell pitch and dopant profile, said combined sinker-channel region is disposed at a depth in said semiconductor substrate extending substantially below an entire body region disposed adjacent to said source region near said top surface wherein said combined sinker-channel region functioning as a buried source-body contact for electrically connecting said body region and said source region to a bottom of said substrate functioning as a source electrode.
2. The BS-LDMOS device of claim 1 further comprising:
a drift region disposed near said top surface under said gate and at a distance away from said source region and extending to and encompassing said drain region.
3. The BS-LDMOS device of claim 2 wherein:
said combined sinker-channel region extending below said drift region wherein said combined sinker-channel region having a dopant conductivity opposite to and compensating said drift region for a reduced source-drain capacitance.
4. The BS-LDMOS device of claim 2 further comprising:
a thick insulation layer disposed on top of said drift region and said drain region for opening a drain contact open therethrough to depositing a drain metal thereon.
5. The BS-LDMOS device of claim 2 wherein:
said gate further comprising spacer for surrounding and insulating sidewalls of said gate.
6. The BS-LDMOS device of claim 2 wherein:
said gate further comprising a terrace gate with a portion of said gate disposed on top of a thick insulation layer.
7. The BS-LDMOS device of claim 2 wherein:
said gate further comprising a gate shield includes a conductive layer covering a gate top surface.
8. The BS-LDMOS device of claim 2 further wherein:
said gate further covered by gate top insulation layer and sidewall spacer layer; and
said BS-LDMOS further comprising a barrier shield layer includes a conductive layer covering said gate top insulation layer, said gate sidewall spacer layer and a top surface of said source region and said body region.
9. The BS-LDMOS device of claim 2 wherein:
a body contact region disposed below a sunken substrate surface surrounded by said source region; and
said BS-LDMOS further comprising a barrier shield layer includes a conductive layer covering a top surface over said source region said over said sunken top surface above said body contact region.
10. The BS-LDMOS device of claim 9 wherein:
said barrier shield layer comprising a conductive layer composed of a TiN/TiSix metallization layer.
11. The BS-LDMOS device of claim 2 wherein:
said semiconductor further comprising an epitaxial layer above a bottom substrate layer wherein said combined sinker-channel region disposed in a lower portion of said epitaxial layer extending downwardly to said bottom substrate layer and extending laterally in said epitaxial layer below said drift region whereby a lateral dimension is reduced with said combined sinker-channel region vertically overlapping with said drift region.
12. The BS-LDMOS device of claim 2 wherein:
said gate further comprising a gate shield includes a conductive layer composed of a TiN/TiSix metallization layer covering a gate top surface.
13. The BS-LDMOS device of claim 2 further comprising:
a thick field oxide layer disposed on top of said drift region and said drain region for opening a drain contact open therethrough to depositing a drain metal thereon to provide a field plate over a drain extension.
14. The BS-LDMOS device of claim 1 wherein:
said source and drain regions are doped with N-type conductivity dopant with said body region and said combined sinker-channel regions doped with a P-type conductivity dopant supported on a P-type substrate.
15. The BS-LDMOS device of claim 1 wherein:
said source and drain regions are doped with P-type conductivity dopant with said body region and said combined sinker-channel regions doped with a N-type conductivity dopant supported on a N-type substrate.