IP Library › Granted Patent US 7,577,813
Granted Patent B2
US 7,577,813 · App. 11/247,036 · Granted Aug 18, 2009

System and method for enumerating multi-level processor-memory affinities for non-uniform memory access systems

Assignee: Dell Products L.P.
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Quick Facts
Patent No.
US 7,577,813
App. No.
11/247,036
Filed
Oct 11, 2005
Granted
Aug 18, 2009
Kind
B2
Art Unit
2188
USPC
711/170
Abstract

A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

Claims (40)

1. A method for enumerating processor-memory affinities for an information-handling system comprising at least two microprocessors and at least two memory units, comprising:

calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system,

performing an algorithm on each processor-memory affinity hierarchy to obtain a processor-memory affinity values for the information-handling system, wherein the processor-memory affinity value is a weighted sum of characteristics in the corresponding processor-memory affinity hierarchy, wherein the algorithm allocates greater weight to characteristics having a greater effect on memory-access speeds than to characteristics having a lesser effect on memory-access speeds, and

populating a table using the processor-memory affinity values obtained by performing the algorithm, wherein an operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

2. The method for enumerating processor-memory affinities for an information-handling system comprising at least two microprocessors and at least two memory units of claim 1 , wherein populating a table using the processor-memory affinity values comprises populating a Static Resource Affinity Table.

3. The method for enumerating processor-memory affinities for an information-handling system comprising at least two microprocessors and at least two memory units of claim 1 , wherein populating a table using the processor-memory affinity values comprises populating a System Locality Information Table.

4. The method for enumerating processor-memory affinities for an information-handling system comprising at least two microprocessors and at least two memory units of claim 1 , wherein calculating a processor-memory affinity hierarchy for the information-handling system for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two characteristics relating to memory-access speed comprises calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using link speeds between the microprocessors in the information-handling system.

5. The method for enumerating processor-memory affinities for an information-handling system comprising at least two microprocessors and at least two memory units of claim 1 , calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two characteristics relating to memory-access speed comprises calculating an processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using a memory size for a memory unit in the information-handling system.

6. The method for enumerating processor-memory affinities for an information-handling system comprising at least two microprocessors and at least two memory units of claim 1 , calculating a processor-memory affinity hierarchy for the information-handling system for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two characteristics relating to memory-access speed comprises calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using a hop count.

7. The method for enumerating processor-memory affinities for an information-handling system comprising at least two microprocessors and at least two memory units of claim 1 , further comprising:

determining that the architecture of the information-handling system has been altered,

recalculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system,

reperforming the algorithm on each processor-memory affinity hierarchy to obtain a new processor-memory affinity values for the information-handling system, wherein the processor-memory affinity value is a weighted sum of characteristics in the corresponding processor-memory affinity hierarchy, wherein the algorithm allocates greater weight to characteristics having a greater effect on memory-access speeds than to characteristics having a lesser effect on memory-access speeds, and

repopulating the table that the operating system in the information-handling system can use to allocate memory units among microprocessors in the information-handling system.

8. A method for efficiently allocating memory units to microprocessors in an information-handling system, comprising:

calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system,

performing an algorithm on each processor-memory affinity hierarchy to obtain a processor-memory affinity values for the information-handling system, wherein the processor-memory affinity value is a weighted sum of characteristics in the corresponding processor-memory affinity hierarchy, wherein the algorithm allocates greater weight to characteristics having a greater effect on memory-access speeds than to characteristics having a lesser effect on memory-access speeds,

populating a table using the processor-memory affinity values obtained by performing the algorithm,

requesting a memory allocation for a microprocessor in the information-handling system,

consulting the table to determine an efficient memory unit allocation for the requesting microprocessor, and

instructing the requesting microprocessor to use a certain memory unit based on the determination of the efficient memory unit allocation.

9. The method for efficiently allocating memory units to microprocessors in an information-handling system of claim 8 , further comprising determining whether a certain memory unit identified for allocation in consulting the table to determine an efficient memory unit allocation is available.

10. The method for efficiently allocating memory units to microprocessors in an information-handling system of claim 9 , further comprising:

consulting the table to determine a next-best efficient memory unit allocation for the requesting microprocessor, if local memory is unavailable.

11. The method for efficiently allocating memory units to microprocessors in an information-handling system of claim 8 , wherein populating a table using the processor-memory affinity values comprises populating at least one of the following: a Static Resource Affinity Table or a System Locality Information Table.

12. The method for efficiently allocating memory units to microprocessors in an information-handling system of claim 9 , wherein calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two factors that affect memory-access speed comprises calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using link speeds between the nodes in the information-handling system.

13. The method for efficiently allocating memory units to microprocessors in an information-handling system of claim 8 , wherein calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two factors that affect memory-access speed comprises calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using a memory size for a memory unit in the information-handling system.

14. The method for efficiently allocating memory units to microprocessors in an information-handling system of claim 8 , wherein calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two factors that affect memory-access speed comprises calculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using a hop count.

15. The method for efficiently allocating memory units to microprocessors in an information-handling system of claim 8 , further comprising:

determining that the architecture of the information-handling system has been altered,

recalculating a processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in the information-handling system using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system,

reperforming the algorithm on the processor-memory affinity hierarchy to obtain a new processor-memory affinity values for the information-handling system, wherein the processor-memory affinity value is a weighted sum of characteristics in the corresponding processor-memory affinity hierarchy, wherein the algorithm allocates greater weight to characteristics having a greater effect on memory-access speeds than to characteristics having a lesser effect on memory-access speeds, and

repopulating the table using the new processor-memory affinity values.

16. A system for enumerating processor-memory affinities in an information-handling system, comprising:

at least two microprocessors, wherein the at least two microprocessors are coupled together,

at least two memory units coupled to the at least two microprocessors,

an operating system located on at least one of the at least two microprocessors, and

a table of processor-memory affinity values stored in the information-handling system that the operating system can use to allocate one or more of the at least two memory units to the at least two microprocessors, wherein each processor-memory affinity value corresponds to a weighted sum of at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system, and wherein the algorithm allocates greater weight to characteristics having a greater effect on memory-access speeds than to characteristics having a lesser effect on memory-access speeds.

17. The system for enumerating processor-memory affinities in an information handling system of claim 16 , wherein each of the at least two microprocessors is associated with at least one local memory unit.

18. The system for enumerating processor-memory affinities in an information handling system of claim 16 , wherein the system comprises at least three microprocessors coupled together, and wherein at least two non-adjacent microprocessors are coupled together.

Assignments (15)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2016
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: DELL MARKETING L.P.; ASAP SOFTWARE EXPRESS, INC.; APPASSURE SOFTWARE, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL INC.; DELL PRODUCTS L.P.; DELL USA L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040040/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2016
From: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: DELL MARKETING L.P.; ASAP SOFTWARE EXPRESS, INC.; APPASSURE SOFTWARE, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL INC.; DELL PRODUCTS L.P.; DELL USA L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040065/0618 →
RELEASE OF SECURITY INTEREST Recorded Sep 13, 2016
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: DELL MARKETING L.P.; ASAP SOFTWARE EXPRESS, INC.; APPASSURE SOFTWARE, INC.; COMPELLANT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL INC.; DELL PRODUCTS L.P.; DELL USA L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040065/0216 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded Jan 2, 2014
From: DELL INC.; APPASSURE SOFTWARE, INC.; ASAP SOFTWARE EXPRESS, INC.; BOOMI, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL USA L.P.; FORCE10 NETWORKS, INC.; GALE TECHNOLOGIES, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 031899/0261 →
PATENT SECURITY AGREEMENT (ABL) Recorded Jan 2, 2014
From: DELL INC.; APPASSURE SOFTWARE, INC.; ASAP SOFTWARE EXPRESS, INC.; BOOMI, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL USA L.P.; FORCE10 NETWORKS, INC.; GALE TECHNOLOGIES, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 031898/0001 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Jan 2, 2014
From: APPASSURE SOFTWARE, INC.; ASAP SOFTWARE EXPRESS, INC.; BOOMI, INC.; COMPELLENT TECHNOLOGIES, INC.; CREDANT TECHNOLOGIES, INC.; DELL INC.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL USA L.P.; FORCE10 NETWORKS, INC.; GALE TECHNOLOGIES, INC.; PEROT SYSTEMS CORPORATION; SECUREWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS FIRST LIEN COLLATERAL AGENT
Reel/Frame 031897/0348 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2005
From: NIJHAWAN, VIJAY B.; WANG, BI-CHONG; GUPTA, SAURABH; WU, WUXIAN
To: DELL PRODUCTS L.P.
Reel/Frame 017088/0097 →
Continuity (1)
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