IP Library Granted Patent US 7,582,921
Granted Patent B2
US 7,582,921 · App. 11/504,738 · Granted Sep 1, 2009

Semiconductor device and method for patterning

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Quick Facts
Patent No.
US 7,582,921
App. No.
11/504,738
Granted
Sep 1, 2009
Kind
B2
Abstract

In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.

Claims (27)

1. A semiconductor device comprising:

a first wiring extending in a first direction and coupled to a plurality of first memory cells;

a second wiring extending in the first direction and coupled to a plurality of second memory cells;

a third wiring extending in the first direction and coupled to a plurality of third memory cells;

a fourth wiring extending in the first direction and coupled to a plurality of fourth memory cells;

a first contact provided at one end of the first wiring;

a second contact provided at one end of the second wiring;

a third contact provided at one end of the third wiring; and

a fourth contact provided at one end of the fourth wiring,

wherein the plurality of first to fourth memory cells are formed in a first rectangular region,

wherein the first and fourth contacts are formed in a second region, wherein the second and third contacts are formed in a third region,

wherein the first rectangular region is provided between the second region and the third region,

wherein a first side of the first rectangular region extends in a second direction perpendicular to the first direction, and

wherein a distance between the other end of the second wiring and the first side of the first rectangular region is shorter than a distance between the other end of the third wiring and the first side of the first rectangular region.

2. A semiconductor device according to claim 1 ,

wherein the other end of the second wiring and the other end of the third wiring are formed in a fourth region, and

wherein the fourth region is provided between the first rectangular region and the second region.

3. A semiconductor device according to claim 1 , wherein a distance between the first contact and the other side of the first rectangular region and a distance between the fourth contact and the other side of the second region are same length.

4. A semiconductor device according to claim 1 , further comprising:

a plurality of sense amplifiers coupled to the first to fourth wirings,

wherein the first to fourth wirings are bit lines.

5. A semiconductor device according to claim 1 , further comprising:

a plurality of word drivers coupled to the first to fourth wirings,

wherein the first to fourth wirings are word lines.

6. A semiconductor device according to claim 1 , wherein a distance between the other end of the second wiring and the other end of the third wiring in the first direction is longer than a distance between the second wiring and the third wiring in the second direction.

7. A semiconductor device according to claim 1 , wherein the plurality of first to fourth memory cells are DRAM memory cells.

8. A semiconductor device according to claim 1 , wherein the second and third wirings are adjacent wirings.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: RENESAS ELECTRONICS CORPORATION
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 032892/0212 →
MERGER AND CHANGE OF NAME Recorded Jul 29, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024755/0338 →