Three-dimensional face-to-face integration assembly
A via for connecting metallization layers of chips bonded in a face-to-face configuration is provided, as well as methods of fabricating the via. The via may function as an interconnection of metallization layers in three-dimensional, stacked, integrated circuits, and may enable high density, low-resistance interconnection formation.
1. A method of forming a via, the method comprising:
bonding a first chip comprising a first metal layer and a second chip comprising a second metal layer in a face-to-face configuration;
after bonding the first chip and the second chip in the face-to-face configuration, thinning a substrate of the first chip; and
after bonding the first chip and the second chip in the face-to-face configuration, forming the via at least partially within the first chip and contacting the second metal layer.
2. The method of claim 1 , wherein thinning the substrate is performed prior to forming the via.
3. The method of claim 1 , wherein the via is formed to electrically contact the first metal layer.
4. The method of claim 1 , further comprising:
forming a hole in the substrate of the first chip; and
wherein forming the via comprises forming a pillar to pass through the hole in the substrate.
5. The method of claim 1 , wherein the via comprises a pillar portion and a nail head portion.
6. The method of claim 5 , wherein the nail head portion is formed such that it is accessible for use as an external contact.
7. The method of claim 1 , wherein the first chip further comprises a collet having an opening, and wherein forming the via comprises forming a pillar so that at least a portion of the pillar passes through the opening of the collet.
8. The method of claim 7 , wherein the via is formed to electrically contact the collet.
9. The method of claim 8 , wherein the collet electrically contacts the first metal layer.
10. The method of claim 1 , wherein bonding the first chip and the second chip in a face-to-face configuration comprises bonding the first chip and the second chip using a bonding layer.
11. The method of claim 10 , wherein the via comprises a pillar portion and a nail head portion, and wherein the pillar portion passes through the bonding layer.
12. The method of claim 1 , wherein thinning the substrate comprises thinning to a stopping layer.
13. The method of claim 12 , wherein the stopping layer comprises a stud.
14. The method of claim 12 , wherein the stopping layer comprises a buried oxide layer.