Implementing virtual packet storage via packet work area
View Patent ↗A method, apparatus and computer program product are provided for implementing virtual packet storage via packet work area (PWA) in a network processor system. A mapping area including a packet work area and a corresponding set of packet segment registers (PSRs) are provided. A PSR is loaded with a Packet ID (PID) and a packet translation unit maps the packet data into the corresponding PWA. The PWA address defining an offset into the packet is translated into a physical address. The packet translation unit redirects loads and stores of the PWA into the correct data buffer or buffers in system memory. Packets include one or more data buffers that are chained together, using a buffer descriptor providing the packet physical address. The buffer descriptor points to a data buffer for the packet and to a next buffer descriptor.
1. A method for implementing virtual packet storage via packet work area in a network processor system comprising the steps of:
providing a mapping area for virtual packet storage, said mapping area including a packet work area (PWA) providing packet data access and virtual addressing to a packet and a corresponding set of packet segment registers;
defining an area of system address space for storing said packet work area (PWA); said area of system address space including a continuous area in real memory,
providing a packet translation unit for translating a PWA address into a physical address;
loading a Packet ID (PID) into one of said packet segment registers;
mapping packet data for said PID into said PWA at a PWA address; said PWA address defining an offset into the packet; said PWA enabling said packet data access and virtual addressing without identifying hardware buffer size or hardware allocation;
said packet translation unit translating said PWA address into said physical address and redirecting loads and stores of said PWA into at least one data buffer in a system memory.
2. The method for implementing virtual packet storage as recited in claim 1 wherein the step of defining an area of system address space for storing said packet work area (PWA) includes the step of providing a packet base address register defining said area of said system address space for storing said packet work area (PWA).
3. The method for implementing virtual packet storage as recited in claim 1 wherein the step of mapping packet data and allocating said packet data in buffers includes providing a buffer descriptor for said packet data.
4. The method for implementing virtual packet storage as recited in claim 3 wherein the step of providing said buffer descriptor includes the steps of storing a pointer in said buffer descriptor to a data buffer, said data buffer for storing said packet data.
5. The method for implementing virtual packet storage as recited in claim 4 further includes the steps of storing a pointer in said buffer descriptor to a next buffer descriptor.
6. A computer storage medium comprising memory storing a computer program product for implementing virtual packet storage via packet work area in a network processor system, said computer program product including a plurality of computer executable instructions stored on said computer storage medium, wherein said instructions, when executed by the network processor system, cause the network processor system to perform the steps of:
providing a mapping area for virtual packet storage, said mapping area including a packet work area (PWA) providing packet data access and virtual addressing to a packet and a corresponding set of packet segment registers;
defining an area of system address space for storing said packet work area (PWA); said area of system address space including a contiguous area in real memory;
providing a packet translation unit for translating a PWA address into a physical address;
loading a Packet ID (PID) into one of said packet segment registers;
mapping packet data for said PID into said PWA at a PWA address; said PWA address defining an offset into the packet; said PWA enabling said packet data access and virtual addressing without identifying hardware buffer size or hardware allocation;
said packet translation unit translating said PWA address into said physical address and redirecting loads and stores of said PWA into at least one data buffer in a system memory.
7. The computer storage medium storing a computer program product for implementing virtual packet storage as recited in claim 6 wherein the step of mapping packet data for said PID into said PWA includes the step of allocating said packet data in buffers.
8. The computer storage medium storing a computer program product for implementing virtual packet storage as recited in claim 7 includes the step of providing a buffer descriptor for said packet data.
9. The computer storage medium storing a computer program product for implementing virtual packet storage as recited in claim 8 wherein the step providing said buffer descriptor for said packet data includes the steps of storing a pointer in said buffer descriptor to a data buffer, said data buffer for storing said packet data; and storing a pointer to a next buffer descriptor.