IP Library Granted Patent US 7,667,321
Granted Patent B2
US 7,667,321 · App. 11/717,227 · Granted Feb 23, 2010

Wire bonding method and related device for high-frequency applications

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Quick Facts
Patent No.
US 7,667,321
App. No.
11/717,227
Granted
Feb 23, 2010
Kind
B2
Abstract

A wire bond circuit device has a circuit die in which substantially all of the input/output (I/O) pads are disposed along the outermost row of pads. A substrate onto which the die is disposed has wedges that are similarly arranged in rows, with the wedges used to carry I/O placed closest to the circuit die. As a result, lowest-tiered bond wire is used to connect the I/O-related pads to their respective wedges.

Claims (35)

1. A method for routing high-frequency signals between a circuit die and a packaging substrate, the circuit die comprising a plurality of pads arranged in a plurality of rows and used to electrically connect the circuit die to the packaging substrate, the circuit die using a total of N of the pads for high-frequency input/output (I/O) and M of the pads for other circuit functions, the method comprising configuring the pads and corresponding substrate wedges so that no more than X of the M pads for other circuit functions are electrically connected to substrate wedges through bond wires that are substantially shorter than the Y shortest bond wires used to electrically connect the N high-frequency I/O pads to corresponding substrate wedges, wherein X is no greater than 10% of N+M and Y is at least 50% of N.

2. The method of claim 1 wherein the X pads are electrically connected to ground or power.

3. The method of claim 1 wherein X is zero and Y equals N.

4. The method of claim 3 wherein the circuit die comprises a total of M+N pads.

5. The method of claim 1 wherein at least Y of the high-frequency I/O pads are disposed along an outermost circumference of the plurality of rows.

6. The method of claim 5 wherein at least Y of the high-frequency I/O pads are connected to corresponding substrate wedges through lowest-tiered bond wires.

7. The method of claim 6 wherein no more than X substrate wedges electrically connected to any of the M pads for other circuit functions are disposed substantially closer to the circuit die than any substrate wedge electrically connected to any of the N high-frequency I/O pads through the Y shortest bond wires that carry high-frequency I/O signals.

8. The method of claim 7 wherein X is zero and Y equals N.

9. The method of claim 5 wherein no more than X substrate wedges electrically connected to any of the M pads for other circuit functions is disposed substantially closer to the circuit die than any substrate wedge electrically connected to any of the N high-frequency I/O pads through the Y shortest bond wires that carry high-frequency I/O signals.

10. The method of claim 9 wherein X is zero and Y equals N.

11. The method of claim 1 wherein the N high-frequency I/O pads carry signals of at least 2 GHz.

12. The method of claim 1 wherein the Y shortest bond wires electrically connected to the N high-frequency I/O pads have respective lengths that are no longer than 2.5 mm.

13. An electronic device comprising:

a packaging substrate comprising a plurality of wedges electrically connected to external conductors of the packaging substrate;

a circuit die disposed on the packaging substrate, the circuit die comprising a plurality of pads arranged in a plurality of rows, a total of N of the pads being used for high-frequency input/output (I/O) and M of the pads for other purposes; and

a plurality of bond wires electrically connecting the pads to the wedges;

wherein no more than X of the M pads for other purposes are electrically connected to corresponding wedges through bond wires that are substantially shorter than the Y shortest bond wires used to electrically connect the N high-frequency I/O pads to corresponding wedges, wherein X is no greater than 10% of N+M and Y is at least 50% of N.

14. The electronic device of claim 13 wherein X is zero and Y equals N.

15. The electronic device of claim 14 wherein the circuit die comprises a total of N+M pads.

16. The electronic device of claim 13 wherein the X pads are electrically connected to ground or power.

17. The electronic device of claim 13 wherein at least Y of the N high-frequency I/O pads are disposed along an outermost circumference of the plurality of rows.

18. The electronic device of claim 17 wherein the bond wires connecting at least Y of the high-frequency I/O pads to the corresponding substrate wedges are lowest-tiered bond wires.

19. The electronic device of claim 18 wherein no more than X substrate wedges electrically connected to any of the M pads for other purposes are disposed substantially closer to the circuit die than any of the substrate wedges electrically connected to the N high-frequency I/O pads.

20. The electronic device of claim 19 wherein X is zero.

21. The electronic device of claim 17 wherein no more than X substrate wedges electrically connected to any of the M pads for other circuit functions are disposed substantially closer to the circuit die than any substrate wedge electrically connected to any of the N high-frequency I/O pads through the Y shortest bond wires.

22. The electronic device of claim 21 wherein X is zero.

23. The electronic device of claim 13 wherein the N high-frequency I/O pads carry signals of at least 2 GHz.

24. A method for routing high-frequency signals between a circuit die and a packaging substrate, the circuit die comprising a plurality of pads, some of the pads being used for high-frequency input/output (I/O) and some of the pads being used for other circuit functions, the pads arranged in a plurality of rows, the method comprising:

disposing substantially all of the pads used for high-frequency I/O into an outermost row of the rows of pads; and

utilizing wire bonds to electrically and physically connect the pads used for high-frequency I/O to corresponding wedges on the substrate.

25. The method of claim 24 further comprising positioning substantially all of the wedges that are electrically and physically coupled to the pads used for high-frequency I/O into an innermost row of wedges on the substrate.

26. The method of claim 24 wherein at least 95% of the pads used for high-frequency I/O are disposed into the outermost row of pads.

27. The method of claim 26 wherein the respective bond wires of the at least 95% of the pads used for high-frequency I/O disposed into the outermost row of pads have lengths that differ from each other by no more than 25%.

28. The method of claim 24 wherein the pads used for high-frequency I/O carry signals of at least 2 GHz.

29. An electronic device formed according to the method of claim 24 .

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 7, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045280/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2007
From: REBELO, ASHLEY; SNIDER, TODD
To: AGERE SYSTEMS, INC.
Reel/Frame 019088/0826 →