Non-volatile memory device and erasing method thereof

1. A non-volatile NAND-flash semiconductor memory device which is configured to execute at least one of a pre-program operation and a post-program operation as part of an erase operation, each of the pre-program and post-program operations of the erase operation including applying a program voltage to a subset only of a plurality of word lines defining a word line block of the memory device before and after erasing memory cells of the word line block, respectively,

wherein the at least one of the pre-program operation and the post-program operations is executed with respect to an upper word line, wherein the upper word line includes at least one word line between a string selection line and a selected word line, wherein the selected word line is applied with a program voltage during a previous program operation.

2. The memory device of claim 1 , wherein a pass voltage is applied to remaining word lines of the word line block during each of the at least one of the pre-program and post-program operations.

3. The memory device of claim 1 , wherein the memory device is configured to execute a local boosting scheme during a normal programming operation.

4. The memory device of claim 1 , wherein the memory device is configured to execute a local boosting scheme during each of at least one of the pre-program and post-program operations.

5. The memory device of claim 1 , wherein the word lines defining the word line block include first through n th word lines, where n is a positive integer, and wherein a normal programming operation is sequentially executed in order from the first word line to the nth word line.

6. The memory device of claim 3 , wherein the word lines defining the word line block include first through n th word lines, where n is a positive integer, and wherein programming progresses from the first word line to the n th word line in the normal programming operation.

7. The memory device of claim 5 , wherein the subset of word lines includes at least the (n-1) th word line.

8. The memory device of claim 5 , wherein each of the subset of word lines is contained among the (n/2) th through n th word lines.

9. The memory device of claim 1 , wherein a same program voltage is applied to each of the subset of word lines in the at least one of the pre-program and post-program operations.

10. The memory device of claim 1 , wherein different program voltages are applied to the subset of word lines in the at least one of the pre-program and post-program operations.

11. The memory device of claim 2 , wherein a same pass voltage is applied to each of the remaining word lines in the at least one of the pre-program and post-program operations.

12. The memory device of claim 2 , wherein different pass voltages are applied to the remaining word lines in the at least of the pre-program and post-program operations.

13. The memory device of claim 1 , wherein the subset of word lines are sequentially arranged one after the other within the word line block.

14. The memory device of claim 1 , wherein the subset of word lines non-sequentially arranged within the word line block.

15. A memory device, comprising:

a memory cell array comprising a plurality of non-volatile memory strings, each of the non-volatile memory strings including a plurality n of non-volatile memory cells, where n is an integer;

a plurality n of word lines intersecting the respective n non-volatile memory cells of each of the non-volatile memory strings;

a decoder configured to apply voltages to the word lines in response to an address;

an erase controller which supplies voltages to the decoder to execute at least one of a pre-program operation and a post-program operation as part of an erase operation, each of the pre-program and post-program operations of the erase operation including applying a program voltage to a subset only of a plurality of word lines defining a word line block of the memory device before and after erasing memory cells of the word line block, respectively,

wherein the at least one of the pre-program operation and the post-program operations is executed with respect to an upper word line, wherein the upper word line includes at least one word line between a string selection line and a selected word line, wherein the selected word line is applied with the program voltage during a previous program operation.

16. An electronic system, comprising a microprocessor operatively coupled to a non-volatile memory device which is configured to execute at least one of a pre-program operation and a post-program operation as part of an erase operation, respectively, each of the pre-program and post-program operations including applying a program voltage to a subset only of a plurality of word lines defining a word line block of the memory device before and after erasing memory cells of the word line block, respectively,

wherein the at least one of the pre-program operation and the post-program operations is executed with respect to an upper word line, wherein the upper word line includes at least one word line between a string selection line and a selected word line, wherein the selected word line is applied with a program voltage during a previous program operation.

17. The electronic device of claim 16 , wherein electronic device is a portable electronic device.

18. The electronic device of claim 16 , wherein the non-volatile memory is contained in a flash memory card.

19. A method of operating a NAND-type flash memory device including providing a program voltage to a subset of word lines of a word line block during at least one of a pre-program and post-program operation executed before or after an erase operation.

20. The method of claim 19 , wherein a pass voltage is applied to remaining word lines of the word line block during the pre-program and post-program operation.

21. The method of claim 19 , further comprising executing a local boosting scheme during a normal programming operation.

22. The memory device of claim 21 , wherein the word lines defining the word line block include first through nth word lines, where n is a positive integer, and wherein the normal programming operation is sequentially executed in order from the first word line to the n th word line.

23. The memory device of claim 22 , wherein the subset of word lines includes at least the (n-1) th word line.

24. The memory device of claim 22 , wherein each of the subset of word lines is contained among the (n/2) th through nth word lines.

25. The memory device of claim 19 , wherein a same program voltage is applied to each of the subset of word lines in the pre-programming and post-programming operations.

26. The memory device of claim 19 , wherein different program voltages are applied to the subset of word lines in the pre-programming and post-programming operation.

27. The memory device of claim 20 , wherein a same pass voltage is applied to each of the remaining word lines in the pre-programming and post-programming operations.

28. The memory device of claim 20 , wherein different pass voltages are applied to the remaining word lines in the pre-programming and post-programming operation.

29. The memory device of claim 19 , wherein the subset of word lines are sequentially arranged one after the other within the word line block.

30. The memory device of claim 19 , wherein the subset of word lines are non-sequentially arranged within the word line block.

31. A method of controlling a NAND-type non-volatile memory device, comprising:

executing an erase operation which includes a pre-program operation in which a program voltage is applied to a first set of word lines of a word line block, and a pass voltage is applied to a remaining set of word lines of the word line block, and

then erasing memory cells of the word line block after the pre-program operation,

wherein the pre-program operation is executed with respect to an upper word line, wherein the upper word line includes at least one word line between a string selection line and a selected word line, wherein the selected word line is applied with the program voltage during a previous program operation.

32. The method of claim 31 , further comprising executing an independent program verify operating for each of the first set of word lines before the erase operation and after the pre-program operation.

33. The method of claim 31 , further comprising executing a program verify operating for all of the first set of word lines before the erase operation and after the pre-program operation.

34. A method of controlling a NAND-type non-volatile memory device, comprising:

executing an erase operation of a word line block which includes erasing memory cells of the word line block, and executing a post-program operation in which a program voltage is applied to a first set of word lines of a word line block, and a pass voltage is applied to a remaining set of word lines of the word line block,

wherein the post-program operation is executed with respect to an upper word line, wherein the upper word line includes at least one word line between a string selection line and a selected word line, wherein the selected word line is applied with the program voltage during a previous program operation.

35. The method of claim 34 , further comprising executing an independent program verify operating for each of the first set of word lines after the post-program operation.

36. The method of claim 35 , further comprising executing a program verify operating for all of the first set of word lines after the post-program operation.