IP Library Granted Patent US 7,674,721
Granted Patent B2
US 7,674,721 · App. 11/797,293 · Granted Mar 9, 2010

Semiconductor device, semiconductor wafer, and methods of producing same device and wafer

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Quick Facts
Patent No.
US 7,674,721
App. No.
11/797,293
Granted
Mar 9, 2010
Kind
B2
Abstract

A method of forming a multi-layered insulation film includes forming a first insulation layer using a first feed gas, the first insulation layer including methyl silsesquioxane (MSQ), forming a second insulation layer using a second feed gas, the second insulation layer including a polysiloxane compound having an Si—H group such that the second insulation layer is in contact with a top of the first insulation layer, and forming a third insulation layer including an inorganic material such that the third insulation layer is in contact with a top of the second insulation layer.

Claims (65)

1. A method of forming a multi-layered insulation film on a semiconductor wafer, comprising:

forming by a plasma CVD method a methyl silsesquioxane (MSQ) layer using a first feed gas;

forming a methylated hydrogen silsesquioxane (MHSQ) layer using a second feed gas, such that the methylated hydrogen silsesquioxane (MHSQ) layer is in contact with a top of the methyl silsesquioxane (MSQ) layer; and

forming an inorganic insulation layer such that the inorganic insulation layer is in contact with a top of the methylated hydrogen silsesquioxane (MHSQ) layer,

wherein said methylated hydrogen silsesquioxane (MHSQ) layer is highly adhesive,

wherein said methylated hydrogen silsesquioxane (MHSQ) layer is formed by a plasma CVD method, said semiconductor wafer being maintained in a plasma atmosphere between said forming said methyl silsesquioxane (MSQ) layer and forming said methylated hydrogen silsesquioxane (MHSQ) layer,

wherein said first feed gas comprises a mixed gas of alkylsilane gas and oxidizing gas, and

wherein said second feed gas comprises a mixed gas of monosilane gas, alkylsilane gas and oxidizing gas.

2. The method of forming a multi-layered methyl silsesquioxane (MSQ) insulation layer on a semiconductor wafer according to claim 1 , forming said methylated hydrogen silsesquioxane (MHSQ) layer and forming said inorganic insulation layer are performed by changing a feed gas composition without removing said semiconductor wafer from said plasma atmosphere.

3. The method of forming a multi-layered insulation film on a semiconductor wafer according to claim 1 , wherein said maintaining said semiconductor wafer in said plasma atmosphere maintains a reactivity of an Si—H group in said methylated hydrogen silsesquioxane (MHSQ) layer and inhibits said methylated hydrogen silsesquioxane (MHSQ) layer from absorbing moisture.

4. The method of forming a multi-layered insulation film on a semiconductor wafer according to claim 1 , wherein said oxidizing gas in said first feed gas and said second feed gas comprises at least one of NO, NO 2 , CO, CO 2 and O 2 .

5. The method of forming a multi-layered insulation film on a semiconductor wafer according to claim 1 , wherein said forming said inorganic insulation layer comprises forming said inorganic insulation layer by plasma CVD.

6. The method of forming a multi-layered insulation film on a semiconductor wafer according to claim 1 , wherein said methyl silsequioxane (MSQ) layer has a thickness which is greater than a thickness of said methylated hydrogen silsesquioxane (MHSQ) layer and greater than a thickness of said inorganic insulation layer.

7. The method of forming a multi-layered insulation film on a semiconductor wafer according to claim 6 , further comprising:

forming a patterned photoresist on said inorganic insulation layer;

etching said MSQ layer, said MHSQ layer and said inorganic insulation layer by using said patterned photo resist, to form a contact hole in said MSQ layer, said MHSQ layer and said inorganic insulation layer;

removing said patterned photoresist by using an oxygen plasma;

forming a copper film in said contact hole; and

planarizing a surface of said copper film and a surface of said inorganic insulation layer by performing chemical mechanical polishing (CMP).

8. The method of forming a multi-layered insulation film on a semiconductor wafer according to claim 6 , wherein said contact hole comprises a plurality of contact holes formed in said MSQ layer, said MHSQ layer and said inorganic insulation layer, and

wherein said copper film comprises a plurality of wires formed in said plurality of contact holes, such that said MSQ layer, MHSQ layer and inorganic insulation layer of said multi-layered insulation film fill a space between said wires, a thickness of said plurality of wires in said grooves being in a range from 200 nm to 500 nm, and

wherein said planarizing a surface of said copper film and a surface of said inorganic insulation layer comprises planarizing a surface of said inorganic insulation layer and a surface of said plurality of wires, said MHSQ layer inhibiting a peeling away of said inorganic insulation layer during said planarization of said surface of said inorganic insulation layer and said plurality of wires.

9. A method of producing a semiconductor device, comprising:

forming, on a semiconductor substrate, a gate electrode with a side-wall insulation layer provided on a side, and a pair of impurity diffusion regions in a surface area of the semiconductor substrate on both sides of the gate electrode;

forming a methyl silsesquioxane (MSQ) layer over an entire surface of said substrate;

forming a methylated hydrogen silsesquioxane (MHSQ) layer which contacts a top of said methyl silsesquioxane (MSQ) layer;

forming an inorganic insulation layer where the inorganic insulation layer contacts a top of said methylated hydrogen silsesquioxane (MHSQ) layer;

after said forming said inorganic insulation layer, etching said MSQ layer, MHSQ layer, and inorganic layer to form a contact hole;

exposing said impurity diffusion regions to a bottom of said contact hole;

exposing said side-wall insulation layer to a side of said contact hole; and

forming an electroconductive film over the entire surface to fill said contact hole,

wherein said methylated hydrogen silsesquioxane (MHSQ) layer is highly adhesive,

wherein a dielectric constant of said methyl silsesquioxane (MSQ) layer is 3.0 or less, and

wherein said forming said methyl silsesquioxane (MSQ) layer and said forming said methylated hydrogen silsesquioxane (MHSQ) layer comprise using plasma chemical vapor deposition (CVD), said device being maintained in a plasma atmosphere between said forming said methyl silsesquioxane (MSQ) layer and said forming said methylated hydrogen silsesquioxane (MHSQ) layer.

10. The method of producing a semiconductor device according to claim 9 , wherein said alkylsilane in said first feed gas and said second feed gas comprises at least one of dimethylsilane, trimethylsilane and tetramethylsilane.

11. The method according to claim 9 , wherein said inorganic layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride.

12. The method according to claim 9 , wherein said methylated hydrogen silsesquioxane (MHSQ) layer includes repeating units shown by formulae I, II and III

and

wherein a molar ratio of II to a total of I, II and III is at least 0.2.

13. The method according to claim 12 , wherein said molar ratio of II to a total of I, II and III is at least 0.5.

14. The method of forming a semiconductor device according to claim 9 , wherein said device is maintained in said plasma atmosphere during an entire period between said forming said methyl silsesquioxane (MSQ) layer and said forming said methylated hydrogen silsesquioxane (MHSQ) second insulation layer.

15. The method of producing a semiconductor device according to claim 9 , wherein forming said gate electrode comprises forming a plurality of gate electrodes having a side-wall insulation layer provided on a side, and a pair of impurity diffusion regions in a surface area of the semiconductor substrate on sides of the gate electrodes, said contact hole being formed between said plurality of gate electrodes,

wherein said forming said methyl silsesquioxane (MSQ) layer comprises forming said methyl silsesquioxane (MSQ) layer on said plurality of gate electrodes,

wherein said forming said methylated hydrogen silsesquioxane (MHSQ) layer comprises forming said methylated hydrogen silsesquioxane (MHSQ) layer on said plurality of gate electrodes, and

wherein said forming said inorganic insulation layer comprises forming said inorganic insulation layer on said plurality of gate electrodes.

16. A method of producing a semiconductor device, comprising:

forming a methyl silsesquioxane (MSQ) layer using a first feed gas, on a semiconductor substrate;

forming a methylated hydrogen silsesquioxane (MHSQ) layer using a second feed gas, where the methylated hydrogen silsesquioxane (MHSQ) layer contacts a top of said methyl silsesquioxane (MSQ) layer;

forming an inorganic insulation layer where the third insulation layer contacts a top of said methylated hydrogen silsesquioxane (MHSQ) layer;

etching said MSQ layer, MHSQ layer and inorganic layer to form recesses therein;

forming an electroconductive film over said recesses in order to fill said recesses; and

removing said electroconductive film formed on the region outside of each of said recesses by at least one of chemical mechanical polishing and etching,

wherein said methylated hydrogen silsesquioxane (MHSQ) layer is highly adhesive,

wherein a dielectric constant of said methyl silsesquioxane (MSQ) layer is 3.0 or less,

wherein said MSQ layer and MHSQ layer are formed by a plasma CVD method, said device being maintained in a plasma atmosphere between said forming said methyl silsesquioxane (MSQ) layer and forming said methylated hydrogen silsesquioxane (MHSQ) layer,

wherein said first feed gas comprises a mixed gas comprising an alkylsilane gas and an oxidizing gas, and

wherein said second feed gas comprises a mixed gas comprising a monosilane gas, an alkylsilane gas and an oxidizing gas.

17. A method of forming a multi-layered insulation film on a semiconductor wafer, comprising:

forming by a plasma CVD method a methyl silsesquioxane (MSQ) layer;

forming a methylated hydrogen silsesquioxane (MHSQ) layer where the methylated hydrogen silsesquioxane (MHSQ) layer contacts a top of the methyl silsesquioxane (MSQ) layer;

forming an inorganic insulation layer where the inorganic insulation layer contacts a top of the methylated hydrogen silsesquioxane (MHSQ) layer; and

after said forming said inorganic insulation layer, forming a plurality of grooves in said MSQ layer, MHSQ layer and inorganic layer,

and

wherein said forming said methylated hydrogen silsesquioxane (MHSQ) layer comprises using a plasma chemical vapor deposition (CVD), said device being maintained in a plasma atmosphere between said forming said methyl silsesquioxane (MSQ) layer and said forming said methylated hydrogen silsesquioxane (MHSQ) layer.

18. The method according to claim 17 , wherein said semiconductor wafer is maintained in a plasma atmosphere during an entire period between said forming said methyl silsesquioxane (MSQ) layer and said forming said methylated hydrogen silsesquioxane (MHSQ) layer.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: RENESAS ELECTRONICS CORPORATION
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 032892/0212 →